ARM: DRA7: Update/Correct MPU and CORE OPP_NOM voltage values

The current OPP_NOM voltage values defined for the MPU and CORE
voltage domains are based on the initial DRA75x_74x_SR1.1_DM data
manual. As per this DM, the PMIC boot voltage can be set to either
1.10V or 1.15V for VD_MPU, and either 1.06V or 1.15V for VD_CORE.
While the current values are correct, the latter set of values
are the values that are common across all DRA75x, DRA72x SoCs and
for all current Silicon revisions. So, update both the MPU and CORE
OPP_NOM voltages to 1.15V.

The macros are also slightly reorganized so that both the MPU and
CORE voltage domain values are defined together.

Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index 38d50d614f3ddc68d208eb29829e2600a2afa92a..9180c67627acbe62ee7241b6210544a51a5be280 100644 (file)
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -240,17 +240,17 @@
 #define VDD_MM_ES2_LOW 880
 
 /* DRA74x/75x voltage settings in mv for OPP_NOM per DM */
-#define VDD_MPU_DRA752         1100
+#define VDD_MPU_DRA752         1150
+#define VDD_CORE_DRA752                1150
 #define VDD_EVE_DRA752         1060
 #define VDD_GPU_DRA752         1060
-#define VDD_CORE_DRA752                1060
 #define VDD_IVA_DRA752         1060
 
 /* DRA72x voltage settings in mv for OPP_NOM per DM */
-#define VDD_MPU_DRA72x         1100
+#define VDD_MPU_DRA72x         1150
+#define VDD_CORE_DRA72x                1150
 #define VDD_EVE_DRA72x         1060
 #define VDD_GPU_DRA72x         1060
-#define VDD_CORE_DRA72x                1060
 #define VDD_IVA_DRA72x         1060
 
 /* Efuse register offsets for DRA7xx platform */