phy: marvell: add support for SFI1

In CP115, comphy4 can be configured into SFI port1
(in addition to SFI0). This patch adds the option
described above.

In addition, rename all existing SFI/XFI references:
COMPHY_TYPE_SFI --> COMPHY_TYPE_SFI0

No functional change for exsiting configuration.

Change-Id: If9176222e0080424ba67347fe4d320215b1ba0c0
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts
index f475fb36107106e86d95b316367e4e11623bf13d..b158f92349173f3ca43c92a37146a4599e425ed9 100644 (file)
--- a/arch/arm/dts/armada-7040-db.dts
+++ b/arch/arm/dts/armada-7040-db.dts
@@ -132,7 +132,8 @@
        };
 
        phy2 {
-               phy-type = <COMPHY_TYPE_SFI>;
+               phy-type = <COMPHY_TYPE_SFI0>;
+               phy-speed = <COMPHY_SPEED_10_3125G>;
        };
 
        phy3 {

diff --git a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
index ce5832c2fbd742eb16d75bc4c242a881bc7d6327..6a586dbbba12c2c5620fbe9b29c91690be0e4c0b 100644 (file)
--- a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
+++ b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
@@ -154,7 +154,7 @@
         * CP0 Serdes Configuration:
         * Lane 0: PCIe0 (x1)
         * Lane 1: Not connected
-        * Lane 2: SFI (10G)
+        * Lane 2: SFI0 (10G)
         * Lane 3: Not connected
         * Lane 4: USB 3.0 host port1 (can be PCIe)
         * Lane 5: Not connected
@@ -166,7 +166,7 @@
                phy-type = <COMPHY_TYPE_UNCONNECTED>;
        };
        phy2 {
-               phy-type = <COMPHY_TYPE_SFI>;
+               phy-type = <COMPHY_TYPE_SFI0>;
        };
        phy3 {
                phy-type = <COMPHY_TYPE_UNCONNECTED>;

diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts
index 1edfaab682ebbcbf63593b2a5bbecbb290afa83e..51c2f23f4dbf56ce80390fba166befebd0e71eda 100644 (file)
--- a/arch/arm/dts/armada-8040-db.dts
+++ b/arch/arm/dts/armada-8040-db.dts
@@ -95,7 +95,7 @@
                phy-type = <COMPHY_TYPE_SATA0>;
        };
        phy2 {
-               phy-type = <COMPHY_TYPE_SFI>;
+               phy-type = <COMPHY_TYPE_SFI0>;
        };
        phy3 {
                phy-type = <COMPHY_TYPE_SATA1>;
@@ -194,7 +194,7 @@
                phy-type = <COMPHY_TYPE_SATA0>;
        };
        phy2 {
-               phy-type = <COMPHY_TYPE_SFI>;
+               phy-type = <COMPHY_TYPE_SFI0>;
        };
        phy3 {
                phy-type = <COMPHY_TYPE_SATA1>;

diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts
index a6ef40138da31b95da22f5c5e149ec78bfcc5c3b..218464831863ee25d12d4f1e118e095d3c288af1 100644 (file)
--- a/arch/arm/dts/armada-8040-mcbin.dts
+++ b/arch/arm/dts/armada-8040-mcbin.dts
@@ -183,7 +183,7 @@
                phy-type = <COMPHY_TYPE_PEX0>;
        };
        phy4 {
-               phy-type = <COMPHY_TYPE_SFI>;
+               phy-type = <COMPHY_TYPE_SFI0>;
        };
        phy5 {
                phy-type = <COMPHY_TYPE_SATA1>;
@@ -299,7 +299,7 @@
                phy-type = <COMPHY_TYPE_SATA1>;
        };
        phy4 {
-               phy-type = <COMPHY_TYPE_SFI>;
+               phy-type = <COMPHY_TYPE_SFI0>;
        };
        phy5 {
                phy-type = <COMPHY_TYPE_SGMII2>;

diff --git a/arch/arm/dts/armada-8040-puzzle-m801.dts b/arch/arm/dts/armada-8040-puzzle-m801.dts
index 0becc4ff0d34f2d1e29b4631a6401c742327632c..510fb84d5a951c5de00b321de7dc117f87861453 100644 (file)
--- a/arch/arm/dts/armada-8040-puzzle-m801.dts
+++ b/arch/arm/dts/armada-8040-puzzle-m801.dts
@@ -234,7 +234,7 @@
                phy-speed = <COMPHY_SPEED_1_25G>;
        };
        phy4 {
-               phy-type = <COMPHY_TYPE_SFI>;
+               phy-type = <COMPHY_TYPE_SFI0>;
        };
        phy5 {
                phy-type = <COMPHY_TYPE_SATA1>;
@@ -380,7 +380,7 @@
                phy-speed = <COMPHY_SPEED_1_25G>;
        };
        phy4 {
-               phy-type = <COMPHY_TYPE_SFI>;
+               phy-type = <COMPHY_TYPE_SFI0>;
        };
        phy5 {
                phy-type = <COMPHY_TYPE_SGMII2>;

diff --git a/arch/arm/dts/cn9130-crb-A.dts b/arch/arm/dts/cn9130-crb-A.dts
index 5c5e0fb2eb1e5386ad12d304a162cfab94890e5d..fcfcd15d8de656e5c91cb6117de2a2fec0e50b60 100644 (file)
--- a/arch/arm/dts/cn9130-crb-A.dts
+++ b/arch/arm/dts/cn9130-crb-A.dts
@@ -31,7 +31,7 @@
        };
 
        phy4 {
-               phy-type = <COMPHY_TYPE_SFI>;
+               phy-type = <COMPHY_TYPE_SFI0>;
                phy-speed = <COMPHY_SPEED_10_3125G>;
        };
 

diff --git a/arch/arm/dts/cn9130-crb-B.dts b/arch/arm/dts/cn9130-crb-B.dts
index 6041084a2c876106f941db251bafa3414606ffa2..b681b6032d6950e2d22e78eca379e7e718aad9f5 100644 (file)
--- a/arch/arm/dts/cn9130-crb-B.dts
+++ b/arch/arm/dts/cn9130-crb-B.dts
@@ -31,7 +31,7 @@
        };
 
        phy4 {
-               phy-type = <COMPHY_TYPE_SFI>;
+               phy-type = <COMPHY_TYPE_SFI0>;
                phy-speed = <COMPHY_SPEED_10_3125G>;
        };
 

diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c
index 9293607926305c2f6a966526eb0dbdaedc4e7574..2c9d7b2288d7eb1c61987276524c4ec42da0b1bf 100644 (file)
--- a/drivers/phy/marvell/comphy_core.c
+++ b/drivers/phy/marvell/comphy_core.c
@@ -41,7 +41,7 @@ static const char *get_type_string(u32 type)
                "UNCONNECTED", "PEX0", "PEX1", "PEX2", "PEX3",
                "SATA0", "SATA1", "SGMII0", "SGMII1", "SGMII2",
                "USB3", "USB3_HOST0", "USB3_HOST1",
-               "USB3_DEVICE", "RXAUI0", "RXAUI1", "SFI", "AP",
+               "USB3_DEVICE", "RXAUI0", "RXAUI1", "SFI0", "SFI1", "AP",
                "IGNORE"
        };
 

diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c
index 349109b6dc089c9e5df8ccdab97720279fb4078a..576538feb70613f5e5ef6be8345e2610ec1a73ef 100644 (file)
--- a/drivers/phy/marvell/comphy_cp110.c
+++ b/drivers/phy/marvell/comphy_cp110.c
@@ -109,10 +109,11 @@ int comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg,
                                 u32 lane)
 {
        int ret;
+       u32 type = ptr_chip_cfg->comphy_map_data[lane].type;
 
        debug_enter();
 
-       if (ptr_chip_cfg->comphy_map_data[lane].type != COMPHY_TYPE_SFI) {
+       if (type != COMPHY_TYPE_SFI0 && type != COMPHY_TYPE_SFI1) {
                pr_err("Comphy %d isn't configured to SFI\n", lane);
                return 0;
        }
@@ -630,13 +631,14 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
                                         ptr_chip_cfg->comphy_base_addr, lane,
                                         mode);
                        break;
-               case COMPHY_TYPE_SFI:
-                       mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE,
-                                               COMPHY_UNIT_ID0,
+               case COMPHY_TYPE_SFI0:
+               case COMPHY_TYPE_SFI1:
+                       /* Calculate SFI id */
+                       id = ptr_comphy_map->type - COMPHY_TYPE_SFI0;
+                       mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE, id,
                                                ptr_comphy_map->speed);
                        ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
-                                        ptr_chip_cfg->comphy_base_addr, lane,
-                                        mode);
+                               ptr_chip_cfg->comphy_base_addr, lane, mode);
                        break;
                case COMPHY_TYPE_RXAUI0:
                case COMPHY_TYPE_RXAUI1:

diff --git a/include/dt-bindings/comphy/comphy_data.h b/include/dt-bindings/comphy/comphy_data.h
index 8e92705989246fce69c995a2905042f3213324d5..8353a7874050bfa4d9840f4f5ee7ff45efc8f489 100644 (file)
--- a/include/dt-bindings/comphy/comphy_data.h
+++ b/include/dt-bindings/comphy/comphy_data.h
@@ -32,10 +32,11 @@
 #define COMPHY_TYPE_USB3_DEVICE                13
 #define COMPHY_TYPE_RXAUI0             14
 #define COMPHY_TYPE_RXAUI1             15
-#define COMPHY_TYPE_SFI                        16
-#define COMPHY_TYPE_AP                 17
-#define COMPHY_TYPE_IGNORE             18
-#define COMPHY_TYPE_MAX                        19
+#define COMPHY_TYPE_SFI0               16
+#define COMPHY_TYPE_SFI1               17
+#define COMPHY_TYPE_AP                 18
+#define COMPHY_TYPE_IGNORE             19
+#define COMPHY_TYPE_MAX                        20
 #define COMPHY_TYPE_INVALID            0xff
 
 #define COMPHY_POLARITY_NO_INVERT      0