Add the core architecture code for the rk3066.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include <asm/arch-rockchip/boot0.h>
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#include <asm/arch-rockchip/gpio.h>
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __ASM_ARCH_TIMER_H__
+#define __ASM_ARCH_TIMER_H__
+
+#endif
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
+config ROCKCHIP_RK3066
+ bool "Support Rockchip RK3066"
+ select CPU_V7A
+ select SPL_BOARD_INIT if SPL
+ select SUPPORT_SPL
+ select SUPPORT_TPL
+ select SPL
+ select TPL
+ select TPL_ROCKCHIP_BACK_TO_BROM
+ select TPL_ROCKCHIP_EARLYRETURN_TO_BROM
+ imply ROCKCHIP_COMMON_BOARD
+ imply SPL_ROCKCHIP_COMMON_BOARD
+ imply SPL_SERIAL
+ imply TPL_ROCKCHIP_COMMON_BOARD
+ imply TPL_SERIAL
+ help
+ The Rockchip RK3066 is a ARM-based SoC with a dual-core Cortex-A9
+ including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
+ video interfaces, several memory options and video codec support.
+ Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
+ UART, SPI, I2C and PWMs.
+
config ROCKCHIP_RK3128
bool "Support Rockchip RK3128"
select CPU_V7A
source "arch/arm/mach-rockchip/px30/Kconfig"
source "arch/arm/mach-rockchip/rk3036/Kconfig"
+source "arch/arm/mach-rockchip/rk3066/Kconfig"
source "arch/arm/mach-rockchip/rk3128/Kconfig"
source "arch/arm/mach-rockchip/rk3188/Kconfig"
source "arch/arm/mach-rockchip/rk322x/Kconfig"
obj-$(CONFIG_ROCKCHIP_PX30) += px30/
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
+obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066/
obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/
obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/
obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x/
--- /dev/null
+if ROCKCHIP_RK3066
+
+config ROCKCHIP_BOOT_MODE_REG
+ default 0x20004040
+
+config SYS_SOC
+ default "rk3066"
+
+config SYS_MALLOC_F_LEN
+ default 0x0800
+
+config SPL_LIBCOMMON_SUPPORT
+ default y
+
+config SPL_LIBGENERIC_SUPPORT
+ default y
+
+config SPL_SERIAL
+ default y
+
+config TPL_LIBCOMMON_SUPPORT
+ default y
+
+config TPL_LIBGENERIC_SUPPORT
+ default y
+
+config TPL_SERIAL
+ default y
+
+endif
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += clk_rk3066.o
+obj-y += rk3066.o
+obj-y += syscon_rk3066.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3066.h>
+#include <linux/err.h>
+
+int rockchip_get_clk(struct udevice **devp)
+{
+ return uclass_get_device_by_driver(UCLASS_CLK,
+ DM_DRIVER_GET(rockchip_rk3066a_cru), devp);
+}
+
+void *rockchip_get_cru(void)
+{
+ struct rk3066_clk_priv *priv;
+ struct udevice *dev;
+ int ret;
+
+ ret = rockchip_get_clk(&dev);
+ if (ret)
+ return ERR_PTR(ret);
+
+ priv = dev_get_priv(dev);
+
+ return priv->cru;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/grf_rk3066.h>
+
+#define GRF_BASE 0x20008000
+
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+ [BROM_BOOTSOURCE_EMMC] = "/mmc@1021c000",
+ [BROM_BOOTSOURCE_SD] = "/mmc@10214000",
+};
+
+void board_debug_uart_init(void)
+{
+ struct rk3066_grf * const grf = (void *)GRF_BASE;
+
+ /* Enable early UART on the RK3066 */
+ rk_clrsetreg(&grf->gpio1b_iomux,
+ GPIO1B1_MASK | GPIO1B0_MASK,
+ GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT |
+ GPIO1B0_UART2_SIN << GPIO1B0_SHIFT);
+}
+
+void spl_board_init(void)
+{
+ if (!IS_ENABLED(CONFIG_SPL_BUILD))
+ return;
+
+ if (IS_ENABLED(CONFIG_SPL_DM_MMC)) {
+ struct rk3066_grf * const grf = (void *)GRF_BASE;
+
+ rk_clrsetreg(&grf->gpio3b_iomux,
+ GPIO3B0_MASK | GPIO3B1_MASK | GPIO3B2_MASK |
+ GPIO3B3_MASK | GPIO3B4_MASK | GPIO3B5_MASK |
+ GPIO3B6_MASK,
+ GPIO3B0_SDMMC0_CLKOUT << GPIO3B0_SHIFT |
+ GPIO3B1_SDMMC0_CMD << GPIO3B1_SHIFT |
+ GPIO3B2_SDMMC0_DATA0 << GPIO3B2_SHIFT |
+ GPIO3B3_SDMMC0_DATA1 << GPIO3B3_SHIFT |
+ GPIO3B4_SDMMC0_DATA2 << GPIO3B4_SHIFT |
+ GPIO3B5_SDMMC0_DATA3 << GPIO3B5_SHIFT |
+ GPIO3B6_SDMMC0_DECTN << GPIO3B6_SHIFT);
+ }
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/clock.h>
+
+static const struct udevice_id rk3066_syscon_ids[] = {
+ { .compatible = "rockchip,rk3066-noc", .data = ROCKCHIP_SYSCON_NOC },
+ { .compatible = "rockchip,rk3066-grf", .data = ROCKCHIP_SYSCON_GRF },
+ { .compatible = "rockchip,rk3066-pmu", .data = ROCKCHIP_SYSCON_PMU },
+ { }
+};
+
+U_BOOT_DRIVER(syscon_rk3066) = {
+ .name = "rk3066_syscon",
+ .id = UCLASS_SYSCON,
+ .of_match = rk3066_syscon_ids,
+};
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+static int rk3066_syscon_bind_of_plat(struct udevice *dev)
+{
+ dev->driver_data = dev->driver->of_match->data;
+ debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(rockchip_rk3066_noc) = {
+ .name = "rockchip_rk3066_noc",
+ .id = UCLASS_SYSCON,
+ .of_match = rk3066_syscon_ids,
+ .bind = rk3066_syscon_bind_of_plat,
+};
+
+U_BOOT_DRIVER(rockchip_rk3066_grf) = {
+ .name = "rockchip_rk3066_grf",
+ .id = UCLASS_SYSCON,
+ .of_match = rk3066_syscon_ids + 1,
+ .bind = rk3066_syscon_bind_of_plat,
+};
+
+U_BOOT_DRIVER(rockchip_rk3066_pmu) = {
+ .name = "rockchip_rk3066_pmu",
+ .id = UCLASS_SYSCON,
+ .of_match = rk3066_syscon_ids + 2,
+ .bind = rk3066_syscon_bind_of_plat,
+};
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define ROCKCHIP_DEVICE_SETTINGS
+#include <configs/rk3066_common.h>
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Google, Inc
+ */
+
+#ifndef __CONFIG_RK3066_COMMON_H
+#define __CONFIG_RK3066_COMMON_H
+
+#include <asm/arch-rockchip/hardware.h>
+#include "rockchip-common.h"
+
+#define CONFIG_SYS_CBSIZE 256
+
+#define CONFIG_SYS_INIT_SP_ADDR 0x78000000
+
+#define CONFIG_IRAM_BASE 0x10080000
+
+#define CONFIG_SPL_MAX_SIZE 0x32000
+
+#define CONFIG_SPL_STACK 0x1008FFFF
+
+#define CONFIG_SYS_SDRAM_BASE 0x60000000
+#define SDRAM_BANK_SIZE (1024UL << 20UL)
+#define SDRAM_MAX_SIZE CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE
+
+#ifndef CONFIG_SPL_BUILD
+
+#define ENV_MEM_LAYOUT_SETTINGS \
+ "scriptaddr=0x60000000\0" \
+ "pxefile_addr_r=0x60100000\0" \
+ "fdt_addr_r=0x61f00000\0" \
+ "kernel_addr_r=0x62000000\0" \
+ "ramdisk_addr_r=0x64000000\0"
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0x6fffffff\0" \
+ "initrd_high=0x6fffffff\0" \
+ "partitions=" PARTS_DEFAULT \
+ ENV_MEM_LAYOUT_SETTINGS \
+ ROCKCHIP_DEVICE_SETTINGS \
+ BOOTENV
+
+#endif /* CONFIG_SPL_BUILD */
+
+#endif
projects / u-boot.git / commitdiff
