]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
Revert "lpc32xx: cpu: add support for soft reset"
authorHarald Seiler <hws@denx.de>
Tue, 15 Dec 2020 15:47:51 +0000 (16:47 +0100)
committerTom Rini <trini@konsulko.com>
Tue, 2 Mar 2021 19:03:02 +0000 (14:03 -0500)
This reverts commit 576007aec9a4a5f4f3dd1f690fb26a8c05ceb75f.

The parameter passed to reset_cpu() no longer holds a meaning as all
call-sites now pass the value 0.  Thus, branching on it is essentially
dead code and will just confuse future readers.

Revert soft-reset support and just always perform a hard-reset for now.
This is a preparation for removal of the reset_cpu() parameter across
the entire tree in a later patch.

Fixes: 576007aec9a4 ("lpc32xx: cpu: add support for soft reset")
Cc: Sylvain Lemieux <slemieux@tycoint.com>
Signed-off-by: Harald Seiler <hws@denx.de>
arch/arm/mach-lpc32xx/cpu.c

index 32af6206056b05890ce7c4f6ab1bc23bcf8feec6..7378192a33c2dcf441769d2fa3367053d59ed9e6 100644 (file)
@@ -22,23 +22,12 @@ void reset_cpu(ulong addr)
        /* Enable watchdog clock */
        setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
 
-       /* To be compatible with the original U-Boot code:
-        * addr: - 0: perform hard reset.
-        *       - !=0: perform a soft reset; i.e. "RESOUT_N" not asserted). */
-       if (addr == 0) {
-               /* Reset pulse length is 13005 peripheral clock frames */
-               writel(13000, &wdt->pulse);
+       /* Reset pulse length is 13005 peripheral clock frames */
+       writel(13000, &wdt->pulse);
 
-               /* Force WDOG_RESET2 and RESOUT_N signal active */
-               writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1
-                      | WDTIM_MCTRL_M_RES2, &wdt->mctrl);
-       } else {
-               /* Force match output active */
-               writel(0x01, &wdt->emr);
-
-               /* Internal reset on match output (no pulse on "RESOUT_N") */
-               writel(WDTIM_MCTRL_M_RES1, &wdt->mctrl);
-       }
+       /* Force WDOG_RESET2 and RESOUT_N signal active */
+       writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 | WDTIM_MCTRL_M_RES2,
+              &wdt->mctrl);
 
        while (1)
                /* NOP */;