]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
mmc: tmio: sdhi: Implement waiting for DAT0 line state
authorMarek Vasut <marek.vasut+renesas@gmail.com>
Sun, 28 Oct 2018 18:28:56 +0000 (19:28 +0100)
committerMarek Vasut <marex@denx.de>
Fri, 2 Nov 2018 15:04:45 +0000 (16:04 +0100)
When the bus switches to 1.8V mode of operation, it is necessary to
verify that the card correctly initiated and completed the voltage
switch. This is done by reading out the state of DATA0 line.

This patch implement support for reading out the state of the DATA0
line, so the MMC core code can correctly switch to 1.8V mode.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
drivers/mmc/renesas-sdhi.c

index e92bbe5f09649d1443c6912e8f0d56d6f8ce127f..63561e19c82bcfbd1b479db0ee75681c98230d27 100644 (file)
@@ -308,13 +308,38 @@ static int renesas_sdhi_set_ios(struct udevice *dev)
        return ret;
 }
 
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
+static int renesas_sdhi_wait_dat0(struct udevice *dev, int state, int timeout)
+{
+       int ret = -ETIMEDOUT;
+       bool dat0_high;
+       bool target_dat0_high = !!state;
+       struct tmio_sd_priv *priv = dev_get_priv(dev);
+
+       timeout = DIV_ROUND_UP(timeout, 10); /* check every 10 us. */
+       while (timeout--) {
+               dat0_high = !!(tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_DAT0);
+               if (dat0_high == target_dat0_high) {
+                       ret = 0;
+                       break;
+               }
+               udelay(10);
+       }
+
+       return ret;
+}
+#endif
+
 static const struct dm_mmc_ops renesas_sdhi_ops = {
        .send_cmd = tmio_sd_send_cmd,
        .set_ios = renesas_sdhi_set_ios,
        .get_cd = tmio_sd_get_cd,
-#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
        .execute_tuning = renesas_sdhi_execute_tuning,
 #endif
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
+       .wait_dat0 = renesas_sdhi_wait_dat0,
+#endif
 };
 
 #define RENESAS_GEN2_QUIRKS    TMIO_SD_CAP_RCAR_GEN2