arm: dts: k3-am68*: Sync with kernel v6.7-rc1

Sync devicetree with kernel v6.7-rc1

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>

diff --git a/arch/arm/dts/k3-am68-sk-base-board.dts b/arch/arm/dts/k3-am68-sk-base-board.dts
index 5df5946687b3483a3d3da932639e85450137771c..1e1a82f9d2b81364e1612dd26172d91b21443444 100644 (file)
--- a/arch/arm/dts/k3-am68-sk-base-board.dts
+++ b/arch/arm/dts/k3-am68-sk-base-board.dts
@@ -553,3 +553,59 @@
                };
        };
 };
+
+&serdes_ln_ctrl {
+       idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_PCIE1_LANE1>,
+                     <J721S2_SERDES0_LANE2_USB_SWAP>, <J721S2_SERDES0_LANE3_USB>;
+};
+
+&serdes_refclk {
+       clock-frequency = <100000000>;
+};
+
+&serdes0 {
+       status = "okay";
+
+       serdes0_pcie_link: phy@0 {
+               reg = <0>;
+               cdns,num-lanes = <2>;
+               #phy-cells = <0>;
+               cdns,phy-type = <PHY_TYPE_PCIE>;
+               resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
+       };
+
+       serdes0_usb_link: phy@2 {
+               status = "okay";
+               reg = <2>;
+               cdns,num-lanes = <1>;
+               #phy-cells = <0>;
+               cdns,phy-type = <PHY_TYPE_USB3>;
+               resets = <&serdes_wiz0 3>;
+       };
+};
+
+&pcie1_rc {
+       status = "okay";
+       reset-gpios = <&exp1 10 GPIO_ACTIVE_HIGH>;
+       phys = <&serdes0_pcie_link>;
+       phy-names = "pcie-phy";
+       num-lanes = <2>;
+};
+
+&usb_serdes_mux {
+       idle-states = <0>; /* USB0 to SERDES lane 2 */
+};
+
+&usbss0 {
+       status = "okay";
+       pinctrl-0 = <&main_usbss0_pins_default>;
+       pinctrl-names = "default";
+       ti,vbus-divider;
+};
+
+&usb0 {
+       dr_mode = "host";
+       maximum-speed = "super-speed";
+       phys = <&serdes0_usb_link>;
+       phy-names = "cdns3,usb3-phy";
+};

diff --git a/arch/arm/dts/k3-am68-sk-som.dtsi b/arch/arm/dts/k3-am68-sk-som.dtsi
index 6c9139f73201a9cb780ef0ca3ae5c3b9cb2d8e29..20861a0a46b0d357b1942f054b043eeff2be7085 100644 (file)
--- a/arch/arm/dts/k3-am68-sk-som.dtsi
+++ b/arch/arm/dts/k3-am68-sk-som.dtsi
@@ -25,6 +25,108 @@
                        reg = <0x00 0x9e800000 0x00 0x01800000>;
                        no-map;
                };
+
+               mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa0000000 0x00 0x100000>;
+                       no-map;
+               };
+
+               mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa0100000 0x00 0xf00000>;
+                       no-map;
+               };
+
+               mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa1000000 0x00 0x100000>;
+                       no-map;
+               };
+
+               mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa1100000 0x00 0xf00000>;
+                       no-map;
+               };
+
+               main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa2000000 0x00 0x100000>;
+                       no-map;
+               };
+
+               main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa2100000 0x00 0xf00000>;
+                       no-map;
+               };
+
+               main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa3000000 0x00 0x100000>;
+                       no-map;
+               };
+
+               main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa3100000 0x00 0xf00000>;
+                       no-map;
+               };
+
+               main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa4000000 0x00 0x100000>;
+                       no-map;
+               };
+
+               main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa4100000 0x00 0xf00000>;
+                       no-map;
+               };
+
+               main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa5000000 0x00 0x100000>;
+                       no-map;
+               };
+
+               main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa5100000 0x00 0xf00000>;
+                       no-map;
+               };
+
+               c71_0_dma_memory_region: c71-dma-memory@a6000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa6000000 0x00 0x100000>;
+                       no-map;
+               };
+
+               c71_0_memory_region: c71-memory@a6100000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa6100000 0x00 0xf00000>;
+                       no-map;
+               };
+
+               c71_1_dma_memory_region: c71-dma-memory@a7000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa7000000 0x00 0x100000>;
+                       no-map;
+               };
+
+               c71_1_memory_region: c71-memory@a7100000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x00 0xa7100000 0x00 0xf00000>;
+                       no-map;
+               };
+
+               rtos_ipc_memory_region: ipc-memories@a8000000 {
+                       reg = <0x00 0xa8000000 0x00 0x01c00000>;
+                       alignment = <0x1000>;
+                       no-map;
+               };
        };
 };
 
@@ -49,3 +151,109 @@
                reg = <0x51>;
        };
 };
+
+&mailbox0_cluster0 {
+       status = "okay";
+       interrupts = <436>;
+       mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+               ti,mbox-rx = <0 0 0>;
+               ti,mbox-tx = <1 0 0>;
+       };
+
+       mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
+               ti,mbox-rx = <2 0 0>;
+               ti,mbox-tx = <3 0 0>;
+       };
+};
+
+&mailbox0_cluster1 {
+       status = "okay";
+       interrupts = <432>;
+       mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+               ti,mbox-rx = <0 0 0>;
+               ti,mbox-tx = <1 0 0>;
+       };
+
+       mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+               ti,mbox-rx = <2 0 0>;
+               ti,mbox-tx = <3 0 0>;
+       };
+};
+
+&mailbox0_cluster2 {
+       status = "okay";
+       interrupts = <428>;
+       mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
+               ti,mbox-rx = <0 0 0>;
+               ti,mbox-tx = <1 0 0>;
+       };
+
+       mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
+               ti,mbox-rx = <2 0 0>;
+               ti,mbox-tx = <3 0 0>;
+       };
+};
+
+&mailbox0_cluster4 {
+       status = "okay";
+       interrupts = <420>;
+       mbox_c71_0: mbox-c71-0 {
+               ti,mbox-rx = <0 0 0>;
+               ti,mbox-tx = <1 0 0>;
+       };
+
+       mbox_c71_1: mbox-c71-1 {
+               ti,mbox-rx = <2 0 0>;
+               ti,mbox-tx = <3 0 0>;
+       };
+};
+
+&mcu_r5fss0_core0 {
+       mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
+       memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
+                       <&mcu_r5fss0_core0_memory_region>;
+};
+
+&mcu_r5fss0_core1 {
+       mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
+       memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
+                       <&mcu_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss0_core0 {
+       mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
+       memory-region = <&main_r5fss0_core0_dma_memory_region>,
+                       <&main_r5fss0_core0_memory_region>;
+};
+
+&main_r5fss0_core1 {
+       mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
+       memory-region = <&main_r5fss0_core1_dma_memory_region>,
+                       <&main_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss1_core0 {
+       mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
+       memory-region = <&main_r5fss1_core0_dma_memory_region>,
+                       <&main_r5fss1_core0_memory_region>;
+};
+
+&main_r5fss1_core1 {
+       mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
+       memory-region = <&main_r5fss1_core1_dma_memory_region>,
+                       <&main_r5fss1_core1_memory_region>;
+};
+
+&c71_0 {
+       status = "okay";
+       mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
+       memory-region = <&c71_0_dma_memory_region>,
+                       <&c71_0_memory_region>;
+};
+
+&c71_1 {
+       status = "okay";
+       mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>;
+       memory-region = <&c71_1_dma_memory_region>,
+                       <&c71_1_memory_region>;
+};

diff --git a/arch/arm/dts/k3-serdes.h b/arch/arm/dts/k3-serdes.h
index 29167f85c1f653d8ffb8ecd6f90b3fd446b05cfe..21b4886c47ba09665acdeb095e9ce6dd90af288c 100644 (file)
--- a/arch/arm/dts/k3-serdes.h
+++ b/arch/arm/dts/k3-serdes.h
@@ -111,7 +111,7 @@
 
 #define J721S2_SERDES0_LANE2_EDP_LANE2         0x0
 #define J721S2_SERDES0_LANE2_PCIE1_LANE2       0x1
-#define J721S2_SERDES0_LANE2_IP3_UNUSED                0x2
+#define J721S2_SERDES0_LANE2_USB_SWAP          0x2
 #define J721S2_SERDES0_LANE2_IP4_UNUSED                0x3
 
 #define J721S2_SERDES0_LANE3_EDP_LANE3         0x0