rockchip: Add core Soc start-up code for rv1108

RV1108 is embedded with an ARM Cortex-A7 single core and a DSP core
from Rockchip. It is designed for varies application scenario such
as car DVR, sports DV, secure camera and UAV camera.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index a8d745ae8a897b68136bd9048f6902f8574a4684..9b2ef2957dd2230b3df0de5321dd6b6540489405 100644 (file)
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -79,6 +79,13 @@ config ROCKCHIP_RK3399
          and video codec support. Peripherals include Gigabit Ethernet,
          USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
 
+config ROCKCHIP_RV1108
+       bool "Support Rockchip RV1108"
+       select CPU_V7
+       help
+         The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
+         and a DSP.
+
 config ROCKCHIP_SPL_BACK_TO_BROM
        bool "SPL returns to bootrom"
        default y if ROCKCHIP_RK3036
@@ -108,4 +115,5 @@ source "arch/arm/mach-rockchip/rk3288/Kconfig"
 source "arch/arm/mach-rockchip/rk3328/Kconfig"
 source "arch/arm/mach-rockchip/rk3368/Kconfig"
 source "arch/arm/mach-rockchip/rk3399/Kconfig"
+source "arch/arm/mach-rockchip/rv1108/Kconfig"
 endif

diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 5ed19c93275946a3a2e5562bb70268e94443e3c3..87d201995e85ac8e6d82419f7b404d310054cb8b 100644 (file)
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -33,3 +33,4 @@ obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
 obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
 obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
 obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
+obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/

diff --git a/arch/arm/mach-rockchip/rv1108/Kconfig b/arch/arm/mach-rockchip/rv1108/Kconfig
new file mode 100644 (file)
index 0000000..40237bb
--- /dev/null
+++ b/arch/arm/mach-rockchip/rv1108/Kconfig
@@ -0,0 +1,9 @@
+if ROCKCHIP_RV1108
+
+config SYS_SOC
+       default "rockchip"
+
+config SYS_MALLOC_F_LEN
+       default 0x400
+
+endif

diff --git a/arch/arm/mach-rockchip/rv1108/Makefile b/arch/arm/mach-rockchip/rv1108/Makefile
new file mode 100644 (file)
index 0000000..9035a1a
--- /dev/null
+++ b/arch/arm/mach-rockchip/rv1108/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2016 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+ifndef CONFIG_SPL_BUILD
+obj-y += syscon_rv1108.o
+endif
+obj-y += rv1108.o
+obj-y += clk_rv1108.o

diff --git a/arch/arm/mach-rockchip/rv1108/clk_rv1108.c b/arch/arm/mach-rockchip/rv1108/clk_rv1108.c
new file mode 100644 (file)
index 0000000..968c356
--- /dev/null
+++ b/arch/arm/mach-rockchip/rv1108/clk_rv1108.c
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * Author: Andy Yan <andy.yan@rock-chips.com>
+ * SPDX-License-Identifier:     GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rv1108.h>
+
+int rockchip_get_clk(struct udevice **devp)
+{
+       return uclass_get_device_by_driver(UCLASS_CLK,
+                       DM_GET_DRIVER(clk_rv1108), devp);
+}
+
+void *rockchip_get_cru(void)
+{
+       struct rv1108_clk_priv *priv;
+       struct udevice *dev;
+       int ret;
+
+       ret = rockchip_get_clk(&dev);
+       if (ret)
+               return ERR_PTR(ret);
+
+       priv = dev_get_priv(dev);
+
+       return priv->cru;
+}

diff --git a/arch/arm/mach-rockchip/rv1108/rv1108.c b/arch/arm/mach-rockchip/rv1108/rv1108.c
new file mode 100644 (file)
index 0000000..868cdd5
--- /dev/null
+++ b/arch/arm/mach-rockchip/rv1108/rv1108.c
@@ -0,0 +1,15 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * Author: Andy Yan <andy.yan@rock-chips.com>
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+       /* Enable D-cache. I-cache is already enabled in start.S */
+       dcache_enable();
+}
+#endif

diff --git a/arch/arm/mach-rockchip/rv1108/syscon_rv1108.c b/arch/arm/mach-rockchip/rv1108/syscon_rv1108.c
new file mode 100644 (file)
index 0000000..8bb0ab8
--- /dev/null
+++ b/arch/arm/mach-rockchip/rv1108/syscon_rv1108.c
@@ -0,0 +1,21 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+
+static const struct udevice_id rv1108_syscon_ids[] = {
+       { .compatible = "rockchip,rv1108-grf", .data = ROCKCHIP_SYSCON_GRF },
+       { }
+};
+
+U_BOOT_DRIVER(syscon_rv1108) = {
+       .name = "rv1108_syscon",
+       .id = UCLASS_SYSCON,
+       .of_match = rv1108_syscon_ids,
+};

diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index 6143f94774b319891bcb49c4d7e22fb172064b0a..a5200d377d129559bf52c89c6ae564686bc56ae6 100644 (file)
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_ROCKCHIP_RK3288) += sysreset_rk3288.o
 obj-$(CONFIG_ROCKCHIP_RK3328) += sysreset_rk3328.o
 obj-$(CONFIG_ROCKCHIP_RK3368) += sysreset_rk3368.o
 obj-$(CONFIG_ROCKCHIP_RK3399) += sysreset_rk3399.o
+obj-$(CONFIG_ROCKCHIP_RV1108) += sysreset_rv1108.o
 obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
 obj-$(CONFIG_ARCH_SNAPDRAGON) += sysreset_snapdragon.o
 obj-$(CONFIG_ARCH_STI) += sysreset_sti.o

diff --git a/drivers/sysreset/sysreset_rv1108.c b/drivers/sysreset/sysreset_rv1108.c
new file mode 100644 (file)
index 0000000..9d8e9f7
--- /dev/null
+++ b/drivers/sysreset/sysreset_rv1108.c
@@ -0,0 +1,46 @@
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ * Author: Andy Yan <andy.yan@rock-chips.com>
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rv1108.h>
+#include <asm/arch/hardware.h>
+#include <linux/err.h>
+
+int rv1108_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+       struct rv1108_cru *cru = rockchip_get_cru();
+
+       if (IS_ERR(cru))
+               return PTR_ERR(cru);
+
+       switch (type) {
+       case SYSRESET_WARM:
+               writel(0xeca8, &cru->glb_srst_snd_val);
+               break;
+       case SYSRESET_COLD:
+               writel(0xfdb9, &cru->glb_srst_fst_val);
+               break;
+       default:
+               return -EPROTONOSUPPORT;
+       }
+
+       return -EINPROGRESS;
+}
+
+static struct sysreset_ops rv1108_sysreset = {
+       .request        = rv1108_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_rv1108) = {
+       .name   = "rv1108_sysreset",
+       .id     = UCLASS_SYSRESET,
+       .ops    = &rv1108_sysreset,
+};

diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h
new file mode 100644 (file)
index 0000000..52750cb
--- /dev/null
+++ b/include/configs/rv1108_common.h
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+#ifndef __CONFIG_RV1108_COMMON_H
+#define __CONFIG_RV1108_COMMON_H
+
+#include <asm/arch/hardware.h>
+#include "rockchip-common.h"
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE                        0x2000
+#define CONFIG_SYS_MAXARGS             16
+#define CONFIG_SYS_MALLOC_LEN          (32 << 20)
+#define CONFIG_SYS_CBSIZE              1024
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_SYS_TIMER_RATE          (24 * 1000 * 1000)
+/* TIMER1,initialized by ddr initialize code */
+#define CONFIG_SYS_TIMER_BASE          0x10350020
+#define CONFIG_SYS_TIMER_COUNTER       (CONFIG_SYS_TIMER_BASE + 8)
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_MEM32
+
+#define CONFIG_SYS_SDRAM_BASE          0x60000000
+#define CONFIG_NR_DRAM_BANKS           1
+#define CONFIG_SYS_TEXT_BASE           CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_TEXT_BASE + 0x100000)
+#define CONFIG_SYS_LOAD_ADDR           (CONFIG_SYS_SDRAM_BASE + 0x2000000)
+
+#endif