#define ZYNQ_GEM_DCFG_DBG6_DMA_64B BIT(23)
+#define MDIO_IDLE_TIMEOUT_MS 100
+
/* Use MII register 1 (MII status register) to detect PHY */
#define PHY_DETECT_REG 1
int err;
err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
- true, 20000, false);
+ true, MDIO_IDLE_TIMEOUT_MS, false);
if (err)
return err;
writel(mgtcr, ®s->phymntnc);
err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
- true, 20000, false);
+ true, MDIO_IDLE_TIMEOUT_MS, false);
if (err)
return err;