config PHY_CORTINA
bool "Cortina Ethernet PHYs support"
+config SYS_CORTINA_NO_FW_UPLOAD
+ bool "Cortina firmware loading support"
+ default n
+ depends on PHY_CORTINA
+ help
+ Cortina phy has provision to store phy firmware in attached dedicated
+ EEPROM. And boards designed with such EEPROM does not require firmware
+ upload.
+
choice
prompt "Location of the Cortina firmware"
default SYS_CORTINA_FW_IN_NOR
* Cortina CS4315/CS4340 10G PHY drivers
*
* Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018, 2020 NXP
*
*/
#error The Cortina PHY needs 10G support
#endif
-#ifndef CORTINA_NO_FW_UPLOAD
+#ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD
struct cortina_reg_config cortina_reg_cfg[] = {
/* CS4315_enable_sr_mode */
{VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
int cs4340_phy_init(struct phy_device *phydev)
{
-#ifndef CORTINA_NO_FW_UPLOAD
+#ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD
int timeout = 100; /* 100ms */
#endif
int reg_value;
* Boards designed with EEPROM attached to Cortina
* does not require FW upload.
*/
-#ifndef CORTINA_NO_FW_UPLOAD
+#ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD
/* step1: BIST test */
phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL, 0x0004);
phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000);
#define AQ_PHY_ADDR3 0x02
#define AQ_PHY_ADDR4 0x03
-#define CORTINA_NO_FW_UPLOAD
#define CORTINA_PHY_ADDR1 0x0
#define INPHI_PHY_ADDR1 0x0
#define AQR107_PHY_ADDR2 0x05
#define AQR107_IRQ_MASK 0x0C
-#define CORTINA_NO_FW_UPLOAD
#define CORTINA_PHY_ADDR1 0x0
#define INPHI_PHY_ADDR1 0x0