#include <usbdevice.h>
#include "ep0.h"
-#include <usb/spr_udc.h>
+#include <usb/designware_udc.h>
#include <asm/arch/hardware.h>
-#include <asm/arch/spr_misc.h>
#define UDC_INIT_MDELAY 80 /* Device settle delay */
/* Some kind of debugging output... */
-#ifndef DEBUG_SPRUSBTTY
+#ifndef DEBUG_DWUSBTTY
#define UDCDBG(str)
#define UDCDBGA(fmt, args...)
#else
}
/*
- * spear_write_noniso_tx_fifo - Write the next packet to TxFIFO.
+ * dw_write_noniso_tx_fifo - Write the next packet to TxFIFO.
* @endpoint: Endpoint pointer.
*
* If the endpoint has an active tx_urb, then the next packet of data from the
* transmitted in this packet.
*
*/
-static void spear_write_noniso_tx_fifo(struct usb_endpoint_instance
+static void dw_write_noniso_tx_fifo(struct usb_endpoint_instance
*endpoint)
{
struct urb *urb = endpoint->tx_urb;
* Handle SETUP USB interrupt.
* This function implements TRM Figure 14-14.
*/
-static void spear_udc_setup(struct usb_endpoint_instance *endpoint)
+static void dw_udc_setup(struct usb_endpoint_instance *endpoint)
{
u8 *datap = (u8 *)&ep0_urb->device_request;
int ep_addr = endpoint->endpoint_address;
endpoint->tx_urb = ep0_urb;
endpoint->sent = 0;
/*
- * Write packet data to the FIFO. spear_write_noniso_tx_fifo
+ * Write packet data to the FIFO. dw_write_noniso_tx_fifo
* will update endpoint->last with the number of bytes written
* to the FIFO.
*/
- spear_write_noniso_tx_fifo(endpoint);
+ dw_write_noniso_tx_fifo(endpoint);
writel(0x0, &inep_regs_p[ep_addr].write_done);
}
/*
* Handle endpoint 0 RX interrupt
*/
-static void spear_udc_ep0_rx(struct usb_endpoint_instance *endpoint)
+static void dw_udc_ep0_rx(struct usb_endpoint_instance *endpoint)
{
u8 dummy[64];
/*
* Handle endpoint 0 TX interrupt
*/
-static void spear_udc_ep0_tx(struct usb_endpoint_instance *endpoint)
+static void dw_udc_ep0_tx(struct usb_endpoint_instance *endpoint)
{
struct usb_device_request *request = &ep0_urb->device_request;
int ep_addr;
* need a zero-length terminating packet.
*/
UDCDBG("ACK control read data stage packet");
- spear_write_noniso_tx_fifo(endpoint);
+ dw_write_noniso_tx_fifo(endpoint);
ep_addr = endpoint->endpoint_address;
writel(0x0, &inep_regs_p[ep_addr].write_done);
}
}
-static struct usb_endpoint_instance *spear_find_ep(int ep)
+static struct usb_endpoint_instance *dw_find_ep(int ep)
{
int i;
* The ep argument is a physical endpoint number for a non-ISO IN endpoint
* in the range 1 to 15.
*/
-static void spear_udc_epn_rx(int ep)
+static void dw_udc_epn_rx(int ep)
{
int nbytes = 0;
struct urb *urb;
- struct usb_endpoint_instance *endpoint = spear_find_ep(ep);
+ struct usb_endpoint_instance *endpoint = dw_find_ep(ep);
if (endpoint) {
urb = endpoint->rcv_urb;
* The ep argument is a physical endpoint number for a non-ISO IN endpoint
* in the range 16 to 30.
*/
-static void spear_udc_epn_tx(int ep)
+static void dw_udc_epn_tx(int ep)
{
- struct usb_endpoint_instance *endpoint = spear_find_ep(ep);
+ struct usb_endpoint_instance *endpoint = dw_find_ep(ep);
/*
* We need to transmit a terminating zero-length packet now if
*/
if (endpoint->tx_urb && endpoint->tx_urb->actual_length) {
/* write data to FIFO */
- spear_write_noniso_tx_fifo(endpoint);
+ dw_write_noniso_tx_fifo(endpoint);
writel(0x0, &inep_regs_p[ep].write_done);
} else if (endpoint->tx_urb
* DEVICE_HUB_CONFIGURED and DEVICE_RESET events here.
* DEVICE_HUB_CONFIGURED causes a transition to the state STATE_POWERED,
* and DEVICE_RESET causes a transition to the state STATE_DEFAULT.
- * The SPEAr USB client controller has the capability to detect when the
+ * The DW USB client controller has the capability to detect when the
* USB cable is connected to a powered USB bus, so we will defer the
* DEVICE_HUB_CONFIGURED and DEVICE_RESET events until later.
*/
/*
* Plug detection interrupt handling
*/
-void spear_udc_plug_irq(void)
+void dw_udc_plug_irq(void)
{
if (readl(&plug_regs_p->plug_state) & PLUG_STATUS_ATTACHED) {
/*
/*
* Device interrupt handling
*/
-void spear_udc_dev_irq(void)
+void dw_udc_dev_irq(void)
{
if (readl(&udc_regs_p->dev_int) & DEV_INT_USBRESET) {
writel(~0x0, &udc_regs_p->endp_int_mask);
/*
* Endpoint interrupt handling
*/
-void spear_udc_endpoint_irq(void)
+void dw_udc_endpoint_irq(void)
{
while (readl(&udc_regs_p->endp_int) & ENDP0_INT_CTRLOUT) {
if ((readl(&outep_regs_p[0].endp_status) & ENDP_STATUS_OUTMSK)
== ENDP_STATUS_OUT_SETUP) {
- spear_udc_setup(udc_device->bus->endpoint_array + 0);
+ dw_udc_setup(udc_device->bus->endpoint_array + 0);
writel(ENDP_STATUS_OUT_SETUP,
&outep_regs_p[0].endp_status);
} else if ((readl(&outep_regs_p[0].endp_status) &
ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_DATA) {
- spear_udc_ep0_rx(udc_device->bus->endpoint_array + 0);
+ dw_udc_ep0_rx(udc_device->bus->endpoint_array + 0);
writel(ENDP_STATUS_OUT_DATA,
&outep_regs_p[0].endp_status);
}
if (readl(&udc_regs_p->endp_int) & ENDP0_INT_CTRLIN) {
- spear_udc_ep0_tx(udc_device->bus->endpoint_array + 0);
+ dw_udc_ep0_tx(udc_device->bus->endpoint_array + 0);
writel(ENDP_STATUS_IN, &inep_regs_p[0].endp_status);
writel(ENDP0_INT_CTRLIN, &udc_regs_p->endp_int);
if ((readl(&outep_regs_p[epnum].endp_status) &
ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_DATA) {
- spear_udc_epn_rx(epnum);
+ dw_udc_epn_rx(epnum);
writel(ENDP_STATUS_OUT_DATA,
&outep_regs_p[epnum].endp_status);
} else if ((readl(&outep_regs_p[epnum].endp_status) &
if (readl(&inep_regs_p[epnum].endp_status) & ENDP_STATUS_IN) {
writel(ENDP_STATUS_IN,
&outep_regs_p[epnum].endp_status);
- spear_udc_epn_tx(epnum);
+ dw_udc_epn_tx(epnum);
writel(ENDP_STATUS_IN,
&outep_regs_p[epnum].endp_status);
* host requests.
*/
while (readl(&plug_regs_p->plug_pending))
- spear_udc_plug_irq();
+ dw_udc_plug_irq();
while (readl(&udc_regs_p->dev_int))
- spear_udc_dev_irq();
+ dw_udc_dev_irq();
if (readl(&udc_regs_p->endp_int))
- spear_udc_endpoint_irq();
+ dw_udc_endpoint_irq();
}
/* Flow control */