This board has not been converted to CONFIG_DM_I2C by the deadline.
Remove it.
Signed-off-by: Tom Rini <trini@konsulko.com>
choice
prompt "NXP LPC32xx board select"
-config TARGET_DEVKIT3250
- bool "Timll DevKit3250"
-
config TARGET_WORK_92105
bool "Work Microwave Work_92105"
endchoice
-source "board/timll/devkit3250/Kconfig"
source "board/work-microwave/work_92105/Kconfig"
source "board/ea/ea-lpc3250devkitv2/Kconfig"
+++ /dev/null
-if TARGET_DEVKIT3250
-
-config SYS_BOARD
- default "devkit3250"
-
-config SYS_VENDOR
- default "timll"
-
-config SYS_CONFIG_NAME
- default "devkit3250"
-
-endif
+++ /dev/null
-DEVKIT3250 BOARD
-M: Vladimir Zapolskiy <vz@mleia.com>
-S: Maintained
-F: board/timll/devkit3250/
-F: include/configs/devkit3250.h
-F: configs/devkit3250_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
-# Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
-
-obj-y := devkit3250.o
-obj-$(CONFIG_SPL_BUILD) += devkit3250_spl.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Embest/Timll DevKit3250 board support
- *
- * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
- */
-
-#include <config.h>
-#include <init.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/emc.h>
-#include <asm/arch/wdt.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct emc_regs *emc = (struct emc_regs *)EMC_BASE;
-static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
-static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE;
-
-void reset_periph(void)
-{
- /* This function resets peripherals by triggering RESOUT_N */
- setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
- writel(WDTIM_MCTRL_RESFRC1, &wdt->mctrl);
- udelay(300);
-
- writel(0, &wdt->mctrl);
- clrbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
-
- /* Such a long delay is needed to initialize SMSC phy */
- udelay(10000);
-}
-
-int board_early_init_f(void)
-{
- lpc32xx_uart_init(CONFIG_CONS_INDEX);
- lpc32xx_i2c_init(1);
- lpc32xx_i2c_init(2);
- lpc32xx_ssp_init();
- lpc32xx_mac_init();
-
- /*
- * nWP may be controlled by GPO19, but unpopulated by default R23
- * makes no sense to configure this GPIO level, nWP is always high
- */
- lpc32xx_slc_nand_init();
-
- return 0;
-}
-
-int board_init(void)
-{
- /* adress of boot parameters */
- gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
-
-#ifdef CONFIG_SYS_FLASH_CFI
- /* Use 16-bit memory interface for NOR Flash */
- emc->stat[0].config = EMC_STAT_CONFIG_PB | EMC_STAT_CONFIG_16BIT;
-
- /* Change the NOR timings to optimum value to get maximum bandwidth */
- emc->stat[0].waitwen = EMC_STAT_WAITWEN(1);
- emc->stat[0].waitoen = EMC_STAT_WAITOEN(0);
- emc->stat[0].waitrd = EMC_STAT_WAITRD(12);
- emc->stat[0].waitpage = EMC_STAT_WAITPAGE(12);
- emc->stat[0].waitwr = EMC_STAT_WAITWR(5);
- emc->stat[0].waitturn = EMC_STAT_WAITTURN(2);
-#endif
-
- return 0;
-}
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
- CFG_SYS_SDRAM_SIZE);
-
- return 0;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Timll DevKit3250 board support, SPL board configuration
- *
- * (C) Copyright 2015 Vladimir Zapolskiy <vz@mleia.com>
- */
-
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/emc.h>
-#include <asm/arch-lpc32xx/gpio.h>
-#include <spl.h>
-
-static struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
-
-/*
- * SDRAM K4S561632N-LC60 settings are selected in assumption that
- * SDRAM clock may be set up to 166 MHz, however at the moment
- * it is 104 MHz. Most delay values are converted to be a multiple of
- * base clock, and precise pinned values are not needed here.
- */
-struct emc_dram_settings dram_64mb = {
- .cmddelay = 0x0001C000,
- .config0 = 0x00005682,
- .rascas0 = 0x00000302,
- .rdconfig = 0x00000011, /* undocumented but crucial value */
-
- .trp = 83333333,
- .tras = 23809524,
- .tsrex = 12500000,
- .twr = 83000000, /* tWR = tRDL = 2 CLK */
- .trc = 15384616,
- .trfc = 15384616,
- .txsr = 12500000,
- .trrd = 1,
- .tmrd = 1,
- .tcdlr = 0,
-
- .refresh = 130000, /* 800 clock cycles */
-
- .mode = 0x00018000,
- .emode = 0x02000000,
-};
-
-void spl_board_init(void)
-{
- /* First of all silence buzzer controlled by GPO_20 */
- writel((1 << 20), &gpio->p3_outp_clr);
-
- lpc32xx_uart_init(CONFIG_CONS_INDEX);
- preloader_console_init();
-
- ddr_init(&dram_64mb);
-
- /*
- * NAND initialization is done by nand_init(),
- * here just enable NAND SLC clocks
- */
- lpc32xx_slc_nand_init();
-}
-
-u32 spl_boot_device(void)
-{
- return BOOT_DEVICE_NAND;
-}
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_SKIP_LOWLEVEL_INIT=y
-CONFIG_SYS_ICACHE_OFF=y
-CONFIG_SYS_DCACHE_OFF=y
-CONFIG_ARCH_CPU_INIT=y
-CONFIG_ARCH_LPC32XX=y
-CONFIG_TEXT_BASE=0x83F00000
-CONFIG_SYS_MALLOC_LEN=0x100000
-CONFIG_SYS_MALLOC_F_LEN=0x400
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80000f20
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0xA0000
-CONFIG_SPL_TEXT_BASE=0x00000000
-CONFIG_SYS_MONITOR_LEN=393216
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_STACK=0xfff8
-CONFIG_SPL=y
-CONFIG_SYS_LOAD_ADDR=0x80008000
-CONFIG_BOOTDELAY=1
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200n8"
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="dhcp; tftp ${loadaddr} ${serverip}:${tftpdir}/${bootfile}; tftp ${dtbaddr} ${serverip}:${tftpdir}/devkit3250.dtb; setenv nfsargs ip=dhcp root=/dev/nfs nfsroot=${serverip}:${nfsroot},tcp; setenv bootargs ${bootargs} ${nfsargs} ${userargs}; bootm ${loadaddr} - ${dtbaddr}"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_MAX_SIZE=0x20000
-CONFIG_SPL_NO_BSS_LIMIT=y
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_NAND_RAW_ONLY=y
-CONFIG_SPL_NAND_DRIVERS=y
-CONFIG_SPL_NAND_ECC=y
-CONFIG_SPL_NAND_SOFTECC=y
-CONFIG_SPL_NAND_SIMPLE=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_NAND=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_SYS_DISABLE_AUTOLOAD=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_USE_BOOTFILE=y
-CONFIG_BOOTFILE="uImage"
-CONFIG_VERSION_VARIABLE=y
-CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
-CONFIG_DMA_LPC32XX=y
-CONFIG_LPC32XX_GPIO=y
-CONFIG_SYS_I2C_LEGACY=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_SYS_I2C_LPC32XX=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_FLASH_SHOW_PROGRESS=0
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_MAX_FLASH_SECT=71
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SYS_NAND_USE_FLASH_BBT=y
-CONFIG_NAND_LPC32XX_SLC=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_SIZE=0x800
-CONFIG_SYS_NAND_OOBSIZE=0x40
-# CONFIG_SYS_NAND_5_ADDR_CYCLE is not set
-CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
-CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
-CONFIG_PHYLIB=y
-CONFIG_PHY_ADDR_ENABLE=y
-CONFIG_PHY_ADDR=31
-CONFIG_PHY_SMSC=y
-CONFIG_RMII=y
-CONFIG_SPECIFY_CONSOLE_INDEX=y
-CONFIG_CONS_INDEX=5
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_USB=y
-CONFIG_SYS_USB_OHCI_SLOT_NAME="lpc32xx-ohci"
-CONFIG_USB_OHCI_LPC32XX=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Embest/Timll DevKit3250 board configuration file
- *
- * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
- */
-
-#ifndef __CONFIG_DEVKIT3250_H__
-#define __CONFIG_DEVKIT3250_H__
-
-/* SoC and board defines */
-#include <linux/sizes.h>
-#include <asm/arch/cpu.h>
-
-/*
- * Memory configurations
- */
-#define CFG_SYS_SDRAM_BASE EMC_DYCS0_BASE
-#define CFG_SYS_SDRAM_SIZE SZ_64M
-
-/*
- * DMA
- */
-
-/*
- * GPIO
- */
-
-/*
- * NOR Flash
- */
-#define CFG_SYS_FLASH_BASE EMC_CS0_BASE
-#define CFG_SYS_FLASH_SIZE SZ_4M
-
-/*
- * NAND controller
- */
-#define CFG_SYS_NAND_BASE SLC_NAND_BASE
-#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
-
-/*
- * NAND chip timings
- */
-#define CFG_LPC32XX_NAND_SLC_WDR_CLKS 14
-#define CFG_LPC32XX_NAND_SLC_WWIDTH 66666666
-#define CFG_LPC32XX_NAND_SLC_WHOLD 200000000
-#define CFG_LPC32XX_NAND_SLC_WSETUP 50000000
-#define CFG_LPC32XX_NAND_SLC_RDR_CLKS 14
-#define CFG_LPC32XX_NAND_SLC_RWIDTH 66666666
-#define CFG_LPC32XX_NAND_SLC_RHOLD 200000000
-#define CFG_LPC32XX_NAND_SLC_RSETUP 50000000
-
-/*
- * USB
- */
-#define CFG_USB_ISP1301_I2C_ADDR 0x2d
-
-/*
- * U-Boot General Configurations
- */
-
-/*
- * Pass open firmware flat tree
- */
-
-/*
- * Environment
- */
-
-#define CFG_EXTRA_ENV_SETTINGS \
- "ethaddr=00:01:90:00:C0:81\0" \
- "dtbaddr=0x81000000\0" \
- "nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0" \
- "tftpdir=vladimir/oe/devkit3250\0" \
- "userargs=oops=panic\0"
-
-/*
- * U-Boot Commands
- */
-
-/* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_TEXT_BASE */
-#define CFG_SYS_NAND_U_BOOT_SIZE 0x60000
-
-#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
-#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
-
-/* See common/spl/spl.c spl_set_header_raw_uboot() */
-
-/*
- * Include SoC specific configuration
- */
-#include <asm/arch/config.h>
-
-#endif /* __CONFIG_DEVKIT3250_H__*/
projects / u-boot.git / commitdiff
