At early U-Boot stage, before relocation, MMU is not yet configured
and disabled. DDR may not be configured with the correct memory
attributes (can be configured in MT_DEVICE instead of MT_MEMORY).
In this case, usage of memcpy_{from, to}io() may leads to synchronous
abort in AARCH64 in case the normal memory address is not 64Bits aligned.
To avoid such situation, forbid usage of normal memory cast to (u64 *) in
case MMU is not enabled.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: mark.kettenis@xs4all.nl
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
return (get_sctlr() & CR_I) != 0;
}
+int mmu_status(void)
+{
+ return (get_sctlr() & CR_M) != 0;
+}
+
void invalidate_icache_all(void)
{
__asm_invalidate_icache_all();
return 0;
}
+int mmu_status(void)
+{
+ return 0;
+}
+
void invalidate_icache_all(void)
{
}
/* Optimized copy functions to read from/write to IO sapce */
#ifdef CONFIG_ARM64
+#include <cpu_func.h>
/*
* Copy data from IO memory space to "real" memory space.
*/
count--;
}
- while (count >= 8) {
- *(u64 *)to = __raw_readq(from);
- from += 8;
- to += 8;
- count -= 8;
+ if (mmu_status()) {
+ while (count >= 8) {
+ *(u64 *)to = __raw_readq(from);
+ from += 8;
+ to += 8;
+ count -= 8;
+ }
}
while (count) {
count--;
}
- while (count >= 8) {
- __raw_writeq(*(u64 *)from, to);
- from += 8;
- to += 8;
- count -= 8;
+ if (mmu_status()) {
+ while (count >= 8) {
+ __raw_writeq(*(u64 *)from, to);
+ from += 8;
+ to += 8;
+ count -= 8;
+ }
}
while (count) {
void dcache_enable(void);
void dcache_disable(void);
void mmu_disable(void);
+int mmu_status(void);
/* arch/$(ARCH)/lib/cache.c */
void enable_caches(void);