mx5: Fix clock gate values

The clock gate values are 2-bit bit-fields. Hence, setting or clearing only one
of these bits like what was done is wrong and can lead to unpredictable behavior
depending on the original value of these bit-fields.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index cba5d1bf0b4eee6414fad047d7cf34e5f1a2bd6e..171d7629ef17e96cdc5e16f2bc7f663df34a342b 100644 (file)
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -101,10 +101,11 @@ void set_usboh3_clk(void)
 
 void enable_usboh3_clk(unsigned char enable)
 {
-       if (enable)
-               setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_USBOH3_60M(1));
-       else
-               clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_USBOH3_60M(1));
+       unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
+
+       clrsetbits_le32(&mxc_ccm->CCGR2,
+                       MXC_CCM_CCGR2_USBOH3_60M(MXC_CCM_CCGR_CG_MASK),
+                       MXC_CCM_CCGR2_USBOH3_60M(cg));
 }
 
 #ifdef CONFIG_I2C_MXC
@@ -132,10 +133,11 @@ void set_usb_phy1_clk(void)
 
 void enable_usb_phy1_clk(unsigned char enable)
 {
-       if (enable)
-               setbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_USB_PHY1(1));
-       else
-               clrbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_USB_PHY1(1));
+       unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
+
+       clrsetbits_le32(&mxc_ccm->CCGR4,
+                       MXC_CCM_CCGR4_USB_PHY1(MXC_CCM_CCGR_CG_MASK),
+                       MXC_CCM_CCGR4_USB_PHY1(cg));
 }
 
 void set_usb_phy2_clk(void)
@@ -145,10 +147,11 @@ void set_usb_phy2_clk(void)
 
 void enable_usb_phy2_clk(unsigned char enable)
 {
-       if (enable)
-               setbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_USB_PHY2(1));
-       else
-               clrbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_USB_PHY2(1));
+       unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
+
+       clrsetbits_le32(&mxc_ccm->CCGR4,
+                       MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK),
+                       MXC_CCM_CCGR4_USB_PHY2(cg));
 }
 
 /*

diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h
index d5eb3033884dca6c4fc90785af49d7f8ccfca371..3b0ed64fc09a53ae80c95760b9835a7f7300555e 100644 (file)
--- a/arch/arm/include/asm/arch-mx5/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx5/crm_regs.h
@@ -285,6 +285,9 @@ struct mxc_ccm_reg {
 
 /* Define the bits in register CCGRx */
 #define MXC_CCM_CCGR_CG_MASK                           0x3
+#define MXC_CCM_CCGR_CG_OFF                            0x0
+#define MXC_CCM_CCGR_CG_RUN_ON                         0x1
+#define MXC_CCM_CCGR_CG_ON                             0x3
 
 #define MXC_CCM_CCGR0_ARM_BUS_OFFSET                   0
 #define MXC_CCM_CCGR0_ARM_BUS(v)                       (((v) & 0x3) << 0)