omap3_spi: introduce CONFIG_OMAP3_SPI_D0_D1_SWAPPED

D0/D1 Swapped or not is a board property, not anything specific to
the am33xx SoC, so add a custom define for it.

At the same time correct the bit handling for the swapped mode
(DPE0 should be cleared and SI/DPE1 set).

Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>

diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index e40a632caa040eba54ee0f2f6549c1da537152af..6791a7e0ec79c495b6fd8ee5f57d257bcd4f1860 100644 (file)
--- a/drivers/spi/omap3_spi.c
+++ b/drivers/spi/omap3_spi.c
@@ -173,14 +173,13 @@ int spi_claim_bus(struct spi_slave *slave)
        /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
         * REVISIT: this controller could support SPI_3WIRE mode.
         */
-#ifdef CONFIG_AM33XX
+#ifdef CONFIG_OMAP3_SPI_D0_D1_SWAPPED
        /*
-        * The reference design on AM33xx has D0 and D1 wired up opposite
-        * of how it has been done on previous platforms.  We assume that
-        * custom hardware will also follow this convention.
+        * Some boards have D0 wired as MOSI / D1 as MISO instead of
+        * The normal D0 as MISO / D1 as MOSI.
         */
-       conf &= OMAP3_MCSPI_CHCONF_DPE0;
-       conf |= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
+       conf &= ~OMAP3_MCSPI_CHCONF_DPE0;
+       conf |= OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1;
 #else
        conf &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
        conf |= OMAP3_MCSPI_CHCONF_DPE0;