armv8/fsl-ch3: Add support to print SoC personality

This patch adds support to print out the SoC personality.
Freescale LS20xx SoCs (compliant to Chassis-3 specifications) can
have 6 personalities: LS2045AE, LS2045A, LS2080AE, LS2080A,
LS2085AE and LS2085A

Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index 19c3995fdf8253a05c28a961b387f9ac572f7775..52bc73177fc66f1a43a642a97d75f475e5ef3a75 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -9,6 +9,7 @@
 #include <asm/system.h>
 #include <asm/armv8/mmu.h>
 #include <asm/io.h>
+#include <asm/arch-fsl-lsch3/soc.h>
 #include <asm/arch-fsl-lsch3/immap_lsch3.h>
 #include <fsl_debug_server.h>
 #include <fsl-mc/fsl_mc.h>
@@ -22,6 +23,35 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static struct cpu_type cpu_type_list[] = {
+#ifdef CONFIG_LS2085A
+       CPU_TYPE_ENTRY(LS2085, LS2085, 8),
+       CPU_TYPE_ENTRY(LS2080, LS2080, 8),
+       CPU_TYPE_ENTRY(LS2045, LS2045, 4),
+#endif
+};
+
+void cpu_name(char *name)
+{
+       struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+       unsigned int i, svr, ver;
+
+       svr = in_le32(&gur->svr);
+       ver = SVR_SOC_VER(svr);
+
+       for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
+               if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
+                       strcpy(name, cpu_type_list[i].name);
+
+                       if (IS_E_PROCESSOR(svr))
+                               strcat(name, "E");
+                       break;
+               }
+
+       if (i == ARRAY_SIZE(cpu_type_list))
+               strcpy(name, "unknown");
+}
+
 #ifndef CONFIG_SYS_DCACHE_OFF
 /*
  * To start MMU before DDR is available, we create MMU table in SRAM.
@@ -380,6 +410,13 @@ int print_cpuinfo(void)
        unsigned int i, core;
        u32 type;
 
+       puts("SoC: ");
+
+       cpu_name(buf);
+       printf(" %s (0x%x)\n", buf, in_le32(&gur->svr));
+
+       memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
+
        get_sys_info(&sysinfo);
        puts("Clock Configuration:");
        for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {

diff --git a/arch/arm/include/asm/arch-fsl-lsch3/soc.h b/arch/arm/include/asm/arch-fsl-lsch3/soc.h
index 16b723d600237782baacc998e42f4877fae77311..9a292720721519354ee36d0c29b9c05acbd2db68 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-lsch3/soc.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/soc.h
@@ -4,5 +4,25 @@
  * SPDX-License-Identifier:    GPL-2.0+
  */
 
+struct cpu_type {
+       char name[15];
+       u32 soc_ver;
+       u32 num_cores;
+};
+
+#define CPU_TYPE_ENTRY(n, v, nc) \
+       { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
+
+#define SVR_WO_E               0xFFFFFE
+#define SVR_LS2045             0x870120
+#define SVR_LS2080             0x870110
+#define SVR_LS2085             0x870100
+
+#define SVR_MAJ(svr)           (((svr) >> 4) & 0xf)
+#define SVR_MIN(svr)           (((svr) >> 0) & 0xf)
+#define SVR_SOC_VER(svr)       (((svr) >> 8) & SVR_WO_E)
+#define IS_E_PROCESSOR(svr)    (!((svr >> 8) & 0x1))
+
 void fsl_lsch3_early_init_f(void);
+void cpu_name(char *name);