armv8: Fix TCR macros for shareability attribute

For ARMv8, outer shareable is 0b10, inner shareable is 0b11 at bit
position [13:12] of TCR_ELx register.

Signed-off-by: Zhichun Hua <zhichun.hua@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>

diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 4b9cb5296572cc9db2d76ffd4193939237da669d..04fa0be64ca346510958adeac33c7af21d59d1ab 100644 (file)
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -93,8 +93,8 @@
 #define TCR_ORGN_WBNWA         (3 << 10)
 #define TCR_ORGN_MASK          (3 << 10)
 #define TCR_SHARED_NON         (0 << 12)
-#define TCR_SHARED_OUTER       (1 << 12)
-#define TCR_SHARED_INNER       (2 << 12)
+#define TCR_SHARED_OUTER       (2 << 12)
+#define TCR_SHARED_INNER       (3 << 12)
 #define TCR_TG0_4K             (0 << 14)
 #define TCR_TG0_64K            (1 << 14)
 #define TCR_TG0_16K            (2 << 14)