powerpc: mpc85xx: Implement CPU erratum A-007907 for secondary cores

Commit 06ad970b53a3 ("powerpc: mpc85xx: Implemente workaround for CPU
erratum A-007907") clears L1CSR2 for the boot core, but other cores
don't run through the workaround. Add similar code for secondary
cores to clear DCSTASHID field in L1CSR2 register.

Signed-off-by: York Sun <york.sun@nxp.com>

diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index 0e0daf5a44ef5b6b324fc2dfe94634df63f02222..e1f12089c33e1139ee957f338d811ab38a0bc2db 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -184,12 +184,18 @@ __secondary_start_page:
 
        mtspr   SPRN_PIR,r4     /* write to PIR register */
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007907
+       mfspr   r8, L1CSR2
+       clrrwi  r8, r8, 10      /* clear bit [54-63] DCSTASHID */
+       mtspr   L1CSR2, r8
+#else
 #ifdef CONFIG_SYS_CACHE_STASHING
        /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
        slwi    r8,r4,1
        addi    r8,r8,32
        mtspr   L1CSR2,r8
 #endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A007907 */
 
 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
        defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)