Xilinx ZynqMP also contains dual Cortex R5 which can run U-Boot.
This patch is adding minimal support to get U-Boot boot.
U-Boot on R5 runs out of DDR with default configuration that's why
DDR needs to be partitioned if there is something else running on arm64.
Console is done via Cadence uart driver and the first Cadence Triple
Timer Counter is used for time.
This configuration with uart1 was tested on zcu100-revC.
U-Boot
2018.05-rc2-00021-gd058a08d907d (Apr 18 2018 - 14:11:27 +0200)
Model: Xilinx ZynqMP R5
DRAM: 512 MiB
WARNING: Caches not enabled
MMC:
In: serial@
ff010000
Out: serial@
ff010000
Err: serial@
ff010000
Net: Net Initialization Skipped
No ethernet found.
ZynqMP r5>
There are two ways how to run this on ZynqMP.
1. Run from ZynqMP arm64
tftpb
20000000 u-boot-r5.elf
setenv autostart no && bootelf -p
20000000
cpu 4 disable && cpu 4 release
10000000 lockstep
or
cpu 4 disable && cpu 4 release
10000000 split
2. Load via jtag when directly to R5
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
F: tools/zynqmp*
N: zynqmp
+ARM ZYNQMP R5
+M: Michal Simek <michal.simek@xilinx.com>
+S: Maintained
+T: git git://git.denx.de/u-boot-microblaze.git
+F: arch/arm/mach-zynqmp-r5/
+
BUILDMAN
M: Simon Glass <sjg@chromium.org>
S: Maintained
imply CMD_SPL
imply ARCH_EARLY_INIT_R
+config ARCH_ZYNQMP_R5
+ bool "Xilinx ZynqMP R5 based platform"
+ select CPU_V7R
+ select OF_CONTROL
+ select DM
+ select DM_SERIAL
+ select CLK
+
config ARCH_ZYNQMP
bool "Xilinx ZynqMP based platform"
select ARM64
source "arch/arm/mach-zynq/Kconfig"
+source "arch/arm/mach-zynqmp-r5/Kconfig"
+
source "arch/arm/cpu/armv7/Kconfig"
source "arch/arm/cpu/armv8/zynqmp/Kconfig"
machine-$(CONFIG_TEGRA) += tegra
machine-$(CONFIG_ARCH_UNIPHIER) += uniphier
machine-$(CONFIG_ARCH_ZYNQ) += zynq
+machine-$(CONFIG_ARCH_ZYNQMP_R5) += zynqmp-r5
machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
zynqmp-zc1751-xm017-dc3.dtb \
zynqmp-zc1751-xm018-dc4.dtb \
zynqmp-zc1751-xm019-dc5.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \
+ zynqmp-r5.dtb
dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb \
am335x-draco.dtb \
am335x-evm.dtb \
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP R5
+ *
+ * (C) Copyright 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "xlnx,zynqmp-r5";
+ model = "Xilinx ZynqMP R5";
+
+ cpus {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-r5";
+ device_type = "cpu";
+ reg = <0>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart1;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x20000000>;
+ };
+
+ chosen {
+ bootargs = "";
+ stdout-path = "serial0:115200n8";
+ };
+
+ clk100: clk100 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ u-boot,dm-pre-reloc;
+ };
+
+ amba {
+ u-boot,dm-pre-reloc;
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ ttc0: timer@ff110000 {
+ compatible = "cdns,ttc";
+ status = "okay";
+ reg = <0xff110000 0x1000>;
+ timer-width = <32>;
+ clocks = <&clk100>;
+ };
+
+ uart1: serial@ff010000 {
+ u-boot,dm-pre-reloc;
+ compatible = "cdns,uart-r1p12", "xlnx,xuartps";
+ reg = <0xff010000 0x1000>;
+ clock-names = "uart_clk", "pclk";
+ clocks = <&clk100 &clk100>;
+ };
+ };
+};
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0
+
+if ARCH_ZYNQMP_R5
+
+config SYS_BOARD
+ string "Board name"
+ default "zynqmp_r5"
+
+config SYS_VENDOR
+ string "Vendor name"
+ default "xilinx"
+
+config SYS_SOC
+ default "zynqmp-r5"
+
+config SYS_CONFIG_NAME
+ string "Board configuration name"
+ default "xilinx_zynqmp_r5"
+ help
+ This option contains information about board configuration name.
+ Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
+ will be used for board configuration.
+
+config SYS_MALLOC_F_LEN
+ default 0x600
+
+endif
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += cpu.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Xilinx, Inc. (Michal Simek)
+ */
+
+#include <common.h>
+#include <asm/armv7_mpu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct mpu_region_config region_config[] = {
+ { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
+ O_I_WB_RD_WR_ALLOC, REGION_1GB },
+ { 0x20000000, REGION_1, XN_EN, PRIV_RO_USR_RO,
+ O_I_WB_RD_WR_ALLOC, REGION_512MB },
+ { 0x40000000, REGION_2, XN_EN, PRIV_RO_USR_RO,
+ O_I_WB_RD_WR_ALLOC, REGION_1GB },
+};
+
+int arch_cpu_init(void)
+{
+ gd->cpu_clk = CONFIG_CPU_FREQ_HZ;
+
+ setup_mpu_regions(region_config, sizeof(region_config) /
+ sizeof(struct mpu_region_config));
+
+ return 0;
+}
+
+/*
+ * Perform the low-level reset.
+ */
+void reset_cpu(ulong addr)
+{
+ while (1)
+ ;
+}
--- /dev/null
+XILINX_ZYNQMP_R5 BOARDS
+M: Michal Simek <michal.simek@xilinx.com>
+S: Maintained
+F: arch/arm/dts/zynqmp-r5*
+F: board/xilinx/zynqmp_r5/
+F: include/configs/xilinx_zynqmp_r5_*
+F: configs/xilinx_zynqmp_r5_*
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0
+#
+# (C) Copyright 2018 Xilinx, Inc. (Michal Simek)
+#
+
+obj-y := board.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2018 Xilinx, Inc. (Michal Simek)
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
+
+int dram_init(void)
+{
+ if (fdtdec_setup_memory_size() != 0)
+ return -EINVAL;
+
+ return 0;
+}
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQMP_R5=y
+CONFIG_SYS_TEXT_BASE=0x10000000
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-r5"
+CONFIG_DEBUG_UART=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SYS_PROMPT="ZynqMP r5> "
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_EMBED=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff010000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_TIMER=y
+CONFIG_CADENCE_TTC_TIMER=y
config ZYNQ_SERIAL
bool "Cadence (Xilinx Zynq) UART support"
- depends on DM_SERIAL && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
+ depends on DM_SERIAL && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_ZYNQMP_R5)
help
This driver supports the Cadence UART. It is found e.g. in Xilinx
Zynq/ZynqMP.
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2018 Xilinx, Inc. (Michal Simek)
+ */
+
+#ifndef __CONFIG_ZYNQMP_R5_H
+#define __CONFIG_ZYNQMP_R5_H
+
+#define CONFIG_EXTRA_ENV_SETTINGS
+
+/* CPU clock */
+#define CONFIG_CPU_FREQ_HZ 500000000
+
+/* Serial drivers */
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+# define CONFIG_ENV_SIZE (128 << 10)
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Boot configuration */
+#define CONFIG_SYS_LOAD_ADDR 0 /* default? */
+
+#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
+
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CONFIG_SYS_MALLOC_LEN 0x1400000
+
+#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+/* Extend size of kernel image for uncompression */
+#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024)
+
+#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* 0x0 - 0x40 is used for placing exception vectors */
+#define CONFIG_SYS_MEMTEST_START 0x40
+#define CONFIG_SYS_MEMTEST_END 0x100
+#define CONFIG_SYS_MEMTEST_SCRATCH 0
+
+#endif /* __CONFIG_ZYNQ_ZYNQMP_R5_H */
projects / u-boot.git / commitdiff
