net: mvpp2x: Remove IRQ configuration from U-Boot

Remove IRQ configuration from U-Boot PP driver.
U-Boot don't use interrupts and configuration of IRQ in U-Boot
caused crashes in Linux shared interrupt mode.
Also interrupt use is redundant in RX routine since a single RX
queue is used.

Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 2e5a1943c1ff739d769248e1f5b76a0960d2831f..3fca987c2943129757d937f82fc89a8408097702 100644 (file)
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -4681,20 +4681,6 @@ static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port)
                port->rxqs[queue] = rxq;
        }
 
-       /* Configure Rx queue group interrupt for this port */
-       if (priv->hw_version == MVPP21) {
-               mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id),
-                           CONFIG_MV_ETH_RXQ);
-       } else {
-               u32 val;
-
-               val = (port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET);
-               mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
-
-               val = (CONFIG_MV_ETH_RXQ <<
-                      MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET);
-               mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
-       }
 
        /* Create Rx descriptor rings */
        for (queue = 0; queue < rxq_number; queue++) {
@@ -5058,25 +5044,6 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
        if (priv->hw_version == MVPP22)
                mvpp2_tx_fifo_init(priv);
 
-       /* Reset Rx queue group interrupt configuration */
-       for (i = 0; i < MVPP2_MAX_PORTS; i++) {
-               if (priv->hw_version == MVPP21) {
-                       mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(i),
-                                   CONFIG_MV_ETH_RXQ);
-                       continue;
-               } else {
-                       u32 val;
-
-                       val = (i << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET);
-                       mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
-
-                       val = (CONFIG_MV_ETH_RXQ <<
-                              MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET);
-                       mvpp2_write(priv,
-                                   MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
-               }
-       }
-
        if (priv->hw_version == MVPP21)
                writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
                       priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
@@ -5222,21 +5189,10 @@ static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
        int pool, rx_bytes, err;
        int rx_received;
        struct mvpp2_rx_queue *rxq;
-       u32 cause_rx_tx, cause_rx, cause_misc;
        u8 *data;
 
-       cause_rx_tx = mvpp2_read(port->priv,
-                                MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
-       cause_rx_tx &= ~MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
-       cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;
-       if (!cause_rx_tx && !cause_misc)
-               return 0;
-
-       cause_rx = cause_rx_tx & MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK;
-
        /* Process RX packets */
-       cause_rx |= port->pending_cause_rx;
-       rxq = mvpp2_get_rx_queue(port, cause_rx);
+       rxq = port->rxqs[0];
 
        /* Get number of received packets and clamp the to-do */
        rx_received = mvpp2_rxq_received(port, rxq->id);