CONFIG_SPL
Enable building of SPL globally.
- CONFIG_SPL_LDSCRIPT
- LDSCRIPT for linking the SPL binary.
-
CONFIG_SPL_MAX_FOOTPRINT
Maximum size in memory allocated to the SPL, BSS included.
When defined, the linker checks that the actual memory
CONFIG_SYS_SPL_MALLOC_SIZE
The size of the malloc pool used in SPL.
- CONFIG_SPL_OS_BOOT
- Enable booting directly to an OS from SPL.
- See also: doc/README.falcon
-
CONFIG_SPL_DISPLAY_PRINT
For ARM, enable an optional function to print more information
about the running system.
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_BOARD_LATE_INIT=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_I2C=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_GO is not set
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_DMA=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl> "
CONFIG_TARGET_MX6DL_MAMOJ=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mamoj"
CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_SPL_DRIVERS_MISC=y
CONFIG_IMX_HAB=y
# CONFIG_CMD_BMODE is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_DMA=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl> "
CONFIG_TARGET_MX6Q_ENGICAM=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore-mipi"
CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0x021f0000
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
+CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_TARGET_MX6Q_ENGICAM=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore"
CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0x020D8024
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
+CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_DMA=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl> "
CONFIG_TARGET_MX6Q_ENGICAM=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore-rqs"
CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
+CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_TARGET_MX6UL_ENGICAM=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam"
CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
+CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="geam6ul> "
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_DMA=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="geam6ul> "
CONFIG_TARGET_MX6UL_ENGICAM=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-isiot-emmc"
CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
+CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="isiotmx6ul> "
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_DMA=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="isiotmx6ul> "
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x600000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mq-evk"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_IMX8MQ_EVK=y
+CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x600000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
CONFIG_DEFAULT_DEVICE_TREE="imx8mq-phanbell"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_IMX8MQ_PHANBELL=y
+CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
CONFIG_HUSH_PARSER=y
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_CMD_EXPORTENV is not set
CONFIG_TARGET_LS1021AIOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SYS_MALLOC_LEN=0x1002000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
CONFIG_SPL_TEXT_BASE=0x10000000
+CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
+CONFIG_SPL_WATCHDOG=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_TARGET_LS1046AQDS=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SYS_MALLOC_LEN=0x102000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_WATCHDOG=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_SYS_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_SYS_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
# CONFIG_SPL_FRAMEWORK is not set
+CONFIG_SPL_NO_CPU_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
# CONFIG_SPL_FRAMEWORK is not set
+CONFIG_SPL_NO_CPU_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DM=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
# CONFIG_SPL_FRAMEWORK is not set
+CONFIG_SPL_NO_CPU_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
# CONFIG_SPL_FRAMEWORK is not set
+CONFIG_SPL_NO_CPU_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DM=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
# CONFIG_SPL_FRAMEWORK is not set
+CONFIG_SPL_NO_CPU_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
# CONFIG_SPL_FRAMEWORK is not set
+CONFIG_SPL_NO_CPU_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x600000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mq-pico-pi"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_PICO_IMX8MQ=y
+CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_CMD_EXPORTENV is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+CONFIG_SPL_OS_BOOT=y
CONFIG_CMD_SPL=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
config SYS_NAND_BLOCK_SIZE
hex "NAND chip eraseblock size"
depends on ARCH_SUNXI || SPL_NAND_SUPPORT || TPL_NAND_SUPPORT
- depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
+ depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && !NAND_FSL_IFC
help
Number of data bytes in one eraseblock for the NAND chip on the
board. This is the multiple of NAND_PAGE_SIZE and the number of
depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
(NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
- depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
+ depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
help
Number of data bytes in one page for the NAND chip on the
board, not including the OOB area.
depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
(NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
- depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
+ depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
help
Number of bytes in the Out-Of-Band area for the NAND chip on
the board.
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x013E000
#define CONFIG_SPL_BSS_START_ADDR 0x00128000
#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
#include <asm/arch/imx-regs.h>
#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_TEXT_BASE 0x0
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x013E000
#define CONFIG_SPL_BSS_START_ADDR 0x00128000
#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
#define CONFIG_SPL_STACK (0x40000000 + ((212 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_I2C
-
#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
/* SPL related MMC defines */
-#define CONFIG_SPL_MMC
#ifdef CONFIG_SPL_BUILD
#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
#endif
/* SPL */
#ifdef CONFIG_SPL
-# ifdef CONFIG_ENV_IS_IN_NAND
-# define CONFIG_SPL_NAND_SUPPORT
-# else
-# define CONFIG_SPL_MMC
-# endif
-
# include "imx6_spl.h"
#endif
#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x960000
#define CONFIG_SPL_BSS_START_ADDR 0x0098FC00
#define CONFIG_SPL_BSS_MAX_SIZE 0x400 /* 1 KB */
#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
-#define CONFIG_SPL_WATCHDOG
-#define CONFIG_SPL_DRIVERS_MISC
-#define CONFIG_SPL_POWER
-#define CONFIG_SPL_I2C
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x187FF0
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_GPIO
-#define CONFIG_SPL_MMC
#define CONFIG_SPL_BSS_START_ADDR 0x00180000
#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
-#define CONFIG_SPL_WATCHDOG
-#define CONFIG_SPL_DRIVERS_MISC
-#define CONFIG_SPL_POWER
-#define CONFIG_SPL_I2C
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x187FF0
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_GPIO
-#define CONFIG_SPL_MMC
#define CONFIG_SPL_BSS_START_ADDR 0x00180000
#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x013E000
#define CONFIG_SPL_BSS_START_ADDR 0x00128000
#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x013E000
#define CONFIG_SPL_BSS_START_ADDR 0x00128000
#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x22050000
#define CONFIG_SPL_BSS_START_ADDR 0x22048000
#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
#define CONFIG_MALLOC_F_ADDR 0x22040000
-#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x95000000 /* SPL_RAM needed */
-
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
#endif
#define SDRAM_CFG_BI 0x00000001
#ifdef CONFIG_SD_BOOT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_I2C
-#define CONFIG_SPL_WATCHDOG
-#define CONFIG_SPL_MMC
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
#define CONFIG_SPL_MAX_SIZE 0x1a000
/* NAND SPL */
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_PBL_PAD
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_WATCHDOG
-#define CONFIG_SPL_I2C
-
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_DRIVERS_MISC
+
#define CONFIG_SPL_MAX_SIZE 0x17000 /* 90 KiB */
#define CONFIG_SPL_STACK 0x1001f000
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
#ifdef CONFIG_SPL
#define CONFIG_SPL_BSS_START_ADDR 0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_MAX_SIZE 0x16000
#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#include "mx6_common.h"
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
#include "imx6_spl.h"
#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x80000)
/* MMC */
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_DRIVERS_MISC
-#endif
-
#endif
#define CONFIG_ARMV7_SECURE_BASE 0x00900000
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_DRIVERS_MISC
-#endif
-
/*
* If we have defined the OPTEE ram size and not OPTEE it means that we were
* launched by OPTEE, because of that we shall skip all the low level
/* SPL */
#ifndef CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_NO_CPU_SUPPORT
#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs"
#endif
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x960000
#define CONFIG_SPL_BSS_START_ADDR 0x98FC00
#define CONFIG_SPL_BSS_MAX_SIZE SZ_1K
#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
-#define CONFIG_SPL_WATCHDOG
-#define CONFIG_SPL_DRIVERS_MISC
-#define CONFIG_SPL_POWER
-#define CONFIG_SPL_I2C
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x187FF0
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_GPIO
-#define CONFIG_SPL_MMC
#define CONFIG_SPL_BSS_START_ADDR 0x00180000
#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
#endif
/* SPL */
-#define CONFIG_SPL_TEXT_BASE 0x200000
#define CONFIG_SPL_MAX_SIZE 0x10000
#define CONFIG_SPL_BSS_START_ADDR 0x20000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_INIT_SP_ADDR 0x301000
-#define CONFIG_SPL_STACK_R
-#define CONFIG_SPL_STACK_R_ADDR CONFIG_SYS_TEXT_BASE
#else
/*
* Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
/* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here
* since it needs to fit in with the other values. By also #defining it
* we get warnings if the Kconfig value mismatches. */
-#define CONFIG_SPL_STACK_R_ADDR 0x2fe00000
#define CONFIG_SPL_BSS_START_ADDR 0x2ff80000
#else
#define SDRAM_OFFSET(x) 0x4##x
/* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here
* since it needs to fit in with the other values. By also #defining it
* we get warnings if the Kconfig value mismatches. */
-#define CONFIG_SPL_STACK_R_ADDR 0x4fe00000
#define CONFIG_SPL_BSS_START_ADDR 0x4ff80000
#endif
#define CONFIG_SPL_MAX_FOOTPRINT CONFIG_SYS_SPI_U_BOOT_OFFS
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-/* No falcon support */
-#undef CONFIG_SPL_OS_BOOT
-
/* FPGA commands that we don't use */
/* Extras */
func(MMC, mmc, 1) \
#ifndef CONFIG_TPL_BUILD
-
-#define CONFIG_SPL_OS_BOOT
-
/* Falcon Mode */
#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
#endif
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU)
-# define CONFIG_SPL_ENV_SUPPORT
# define CONFIG_SPL_HASH
# define CONFIG_ENV_MAX_ENTRIES 10
#endif