This can be overridden at run-time by setting the bootm_boot_mode env.
variable to "sec" or "nonsec".
+config HAS_ARMV7_SECURE_BASE
+ bool "Enable support for a ahardware secure memory area"
+ default y if ARCH_LS1021A || ARCH_MX7 || ARCH_MX7ULP || ARCH_STM32MP \
+ || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || TEGRA124
+
+config ARMV7_SECURE_BASE
+ hex "Base address for secure mode memory"
+ depends on HAS_ARMV7_SECURE_BASE
+ default 0xfff00000 if TEGRA124
+ default 0x2ffc0000 if ARCH_STM32MP
+ default 0x2f000000 if ARCH_MX7ULP
+ default 0x10010000 if ARCH_LS1021A
+ default 0x00900000 if ARCH_MX7
+ default 0x00044000 if MACH_SUN8I
+ default 0x00020000 if MACH_SUN6I || MACH_SUN7I
+
+config ARMV7_SECURE_RESERVE_SIZE
+ hex
+ depends on TEGRA124 && HAS_ARMV7_SECURE_BASE
+ default 0x100000
+ help
+ Reserve top 1M for secure RAM
+
+config ARMV7_SECURE_MAX_SIZE
+ hex
+ depends on ARMV7_SECURE_BASE && ARCH_STM32MP || MACH_SUN6I \
+ || MACH_SUN7I || MACH_SUN8I
+ default 0xbc00 if MACH_SUN8I && !MACH_SUN8I_H3
+ default 0x3c00 if MACH_SUN8I && MACH_SUN8I_H3
+ default 0x10000
+
config ARMV7_VIRT
bool "Enable support for hardware virtualization" if EXPERT
depends on CPU_V7_HAS_VIRT && ARMV7_NONSEC
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB1_VBUS_PIN="PH23"
CONFIG_USB2_VBUS_PIN="PH23"
+# CONFIG_HAS_ARMV7_SECURE_BASE is not set
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SPL=y
CONFIG_MACH_SUN8I_V3S=y
CONFIG_DRAM_CLK=360
+# CONFIG_HAS_ARMV7_SECURE_BASE is not set
# CONFIG_NETDEVICES is not set
CONFIG_DRAM_CLK=576
CONFIG_MMC0_CD_PIN="PH13"
CONFIG_USB1_VBUS_PIN="PH23"
+# CONFIG_HAS_ARMV7_SECURE_BASE is not set
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
CONFIG_TARGET_MX7ULP_EVK=y
+# CONFIG_HAS_ARMV7_SECURE_BASE is not set
CONFIG_SYS_LOAD_ADDR=0x60800000
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
CONFIG_TARGET_MX7ULP_EVK=y
+# CONFIG_HAS_ARMV7_SECURE_BASE is not set
CONFIG_SYS_LOAD_ADDR=0x60800000
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; fi; fi; fi"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020
CONFIG_SYS_CLK_FREQ=66666666
+# CONFIG_HAS_ARMV7_SECURE_BASE is not set
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-pg-wcom-expu1"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020
+# CONFIG_HAS_ARMV7_SECURE_BASE is not set
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020
CONFIG_SYS_CLK_FREQ=66666666
+# CONFIG_HAS_ARMV7_SECURE_BASE is not set
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-pg-wcom-seli8"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020
+# CONFIG_HAS_ARMV7_SECURE_BASE is not set
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_DRAM_CLK=504
CONFIG_DRAM_ODT_EN=y
CONFIG_I2C0_ENABLE=y
+# CONFIG_HAS_ARMV7_SECURE_BASE is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
-/* Reserve top 1M for secure RAM */
-#define CONFIG_ARMV7_SECURE_BASE 0xfff00000
-#define CONFIG_ARMV7_SECURE_RESERVE_SIZE 0x00100000
-
#endif /* __CONFIG_H */
#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
-/* Reserve top 1M for secure RAM */
-#define CONFIG_ARMV7_SECURE_BASE 0xfff00000
-#define CONFIG_ARMV7_SECURE_RESERVE_SIZE 0x00100000
-
#endif /* __CONFIG_H */
#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
-/* Reserve top 1M for secure RAM */
-#define CONFIG_ARMV7_SECURE_BASE 0xfff00000
-#define CONFIG_ARMV7_SECURE_RESERVE_SIZE 0x00100000
-
#endif /* __CONFIG_H */
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
-
#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
-
#define CONFIG_DEEP_SLEEP
#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
-
#define CONFIG_DEEP_SLEEP
#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
-
#define CONFIG_DEEP_SLEEP
#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
/* MMC */
-#define CONFIG_ARMV7_SECURE_BASE 0x00900000
-
/*
* If we have defined the OPTEE ram size and not OPTEE it means that we were
* launched by OPTEE, because of that we shall skip all the low level
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-#define CONFIG_ARMV7_SECURE_BASE 0x2F000000
-
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#endif /* __CONFIG_H */
#include <linux/sizes.h>
#include <asm/arch/stm32.h>
-#ifdef CONFIG_ARMV7_PSCI
-/* PSCI support */
-#define CONFIG_ARMV7_SECURE_BASE STM32_SYSRAM_BASE
-#define CONFIG_ARMV7_SECURE_MAX_SIZE STM32_SYSRAM_SIZE
-#endif
-
/*
* Configuration of the external SRAM memory used by U-Boot
*/
#ifndef __CONFIG_H
#define __CONFIG_H
-/*
- * A31 specific configuration
- */
-
-#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE
-#define CONFIG_ARMV7_SECURE_MAX_SIZE (64 * 1024) /* 64 KB */
-
/*
* Include common sunxi configuration where most the settings are
*/
#ifndef __CONFIG_H
#define __CONFIG_H
-/*
- * A20 specific configuration
- */
-
-#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE
-#define CONFIG_ARMV7_SECURE_MAX_SIZE (64 * 1024) /* 64 KB */
-
/*
* Include common sunxi configuration where most the settings are
*/
#include <asm/arch/cpu.h>
-#ifdef SUNXI_SRAM_A2_SIZE
-/*
- * If the SoC has enough SRAM A2, use that for the secure monitor.
- * Skip the first 16 KiB of SRAM A2, which is not usable, as only certain bytes
- * are writable. Reserve the last 17 KiB for the resume shim and SCP firmware.
- */
-#define CONFIG_ARMV7_SECURE_BASE (SUNXI_SRAM_A2_BASE + 16 * 1024)
-#define CONFIG_ARMV7_SECURE_MAX_SIZE (SUNXI_SRAM_A2_SIZE - 33 * 1024)
-#endif
-
/*
* Include common sunxi configuration where most the settings are
*/