x86: acpi: Create a common irqlinks ASL file

Move the irqlinks.asl file currently in the BayTrail directory to
a common place to be shared among all x86 platforms. As the PIRQ
routing control programming interface is common to Intel chipsets,
leave the common part in the common file, and move the platform
specific part to the platform files.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl b/arch/x86/include/asm/acpi/irqlinks.asl
similarity index 92%
rename from arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl
rename to arch/x86/include/asm/acpi/irqlinks.asl
index 0affa2335c842fb9832f7d80d2de29d0c30d1cbd..84c1e53c7de6453e3f4e9438f41a05747df33b28 100644 (file)
--- a/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl
+++ b/arch/x86/include/asm/acpi/irqlinks.asl
@@ -7,26 +7,19 @@
  * SPDX-License-Identifier:    GPL-2.0+
  */
 
-Scope (\)
-{
-       /* Intel Legacy Block */
-       OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
-       Field(ILBS, AnyAcc, NoLock, Preserve) {
-               Offset (0x8),
-               PRTA, 8,
-               PRTB, 8,
-               PRTC, 8,
-               PRTD, 8,
-               PRTE, 8,
-               PRTF, 8,
-               PRTG, 8,
-               PRTH, 8,
-               Offset (0x88),
-                   , 3,
-               UI3E, 1,
-               UI4E, 1
-       }
-}
+/*
+ * Intel chipset PIRQ routing control ASL description
+ *
+ * The programming interface is common to most Intel chipsets. But the PRTx
+ * registers may be mapped to different blocks. Some chipsets map them to LPC
+ * device (00:1f:00) PCI configuration space (like TunnelCreek, Quark), while
+ * some newer Atom SoCs (like BayTrail, Braswell) map them to Intel Legacy
+ * Block (ILB) memory space.
+ *
+ * This file defines 8 PCI IRQ link devices which corresponds to 8 PIRQ lines
+ * PIRQ A/B/C/D/E/F/G/H. To incorperate this file, the PRTx registers must be
+ * defined somewhere else in the platform's ASL files.
+ */
 
 Device (LNKA)
 {

diff --git a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
index 385671c9688167d17fd43eb15ddef716212adfc7..22f0d68f4dd5df100a38332595c31d9718075793 100644 (file)
--- a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
+++ b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
@@ -10,6 +10,27 @@
 
 /* Intel LPC Bus Device - 0:1f.0 */
 
+Scope (\)
+{
+       /* Intel Legacy Block */
+       OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
+       Field(ILBS, AnyAcc, NoLock, Preserve) {
+               Offset (0x8),
+               PRTA, 8,
+               PRTB, 8,
+               PRTC, 8,
+               PRTD, 8,
+               PRTE, 8,
+               PRTF, 8,
+               PRTG, 8,
+               PRTH, 8,
+               Offset (0x88),
+                   , 3,
+               UI3E, 1,
+               UI4E, 1
+       }
+}
+
 Device (LPCB)
 {
        Name(_ADR, 0x001f0000)
@@ -23,7 +44,7 @@ Device (LPCB)
                Offset(0x84)
        }
 
-       #include "irqlinks.asl"
+       #include <asm/acpi/irqlinks.asl>
 
        /* Firmware Hub */
        Device (FWH)