select SPL_SYS_NO_VECTOR_TABLE if SPL
select ARCH_VERY_EARLY_INIT
select ARMADA_32BIT_SYSCON_RESET if DM_RESET && PCI_MVEBU
+ select ARMADA_32BIT_SYSCON_SYSRESET if SYSRESET
# ARMv7 SoCs...
config ARMADA_375
default 0x0
depends on MVEBU_SPL_BOOT_DEVICE_SPI
+config ARMADA_32BIT_SYSCON
+ bool
+ depends on ARMADA_32BIT
+ select REGMAP
+ select SYSCON
+
config ARMADA_32BIT_SYSCON_RESET
bool "Support Armada XP/375/38x/39x reset controller"
depends on ARMADA_32BIT
depends on DM_RESET
- select REGMAP
- select SYSCON
+ select ARMADA_32BIT_SYSCON
help
Build support for Armada XP/375/38x/39x reset controller. This is
needed for PCIe support.
+config ARMADA_32BIT_SYSCON_SYSRESET
+ bool "Support Armada XP/375/38x/39x sysreset via driver model"
+ depends on ARMADA_32BIT
+ depends on SYSRESET
+ select ARMADA_32BIT_SYSCON
+ help
+ Build support for Armada XP/375/38x/39x system reset via driver model.
+
source "board/solidrun/clearfog/Kconfig"
source "board/kobol/helios4/Kconfig"
#include <regmap.h>
#include <reset-uclass.h>
#include <syscon.h>
+#include <sysreset.h>
#include <asm/io.h>
-#define MVEBU_SOC_CONTROL_1_REG 0x4
+#define MVEBU_SOC_CONTROL_1_REG 0x4
-#define MVEBU_PCIE_ID 0
+#if defined(CONFIG_ARMADA_375)
+# define MVEBU_RSTOUTN_MASK_REG 0x54
+# define MVEBU_SYS_SOFT_RST_REG 0x58
+#else
+# define MVEBU_RSTOUTN_MASK_REG 0x60
+# define MVEBU_SYS_SOFT_RST_REG 0x64
+#endif
+
+#define MVEBU_GLOBAL_SOFT_RST_BIT BIT(0)
+
+#define MVEBU_PCIE_ID 0
+
+#if IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_RESET)
static int mvebu_reset_of_xlate(struct reset_ctl *rst,
struct ofnode_phandle_args *args)
.ops = &mvebu_reset_ops,
};
+#endif /* IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_RESET) */
+
+#if IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_SYSRESET)
+
+static int mvebu_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+ struct regmap *regmap = syscon_get_regmap(dev->parent);
+ uint bit;
+
+ if (type != SYSRESET_COLD)
+ return -EPROTONOSUPPORT;
+
+ bit = MVEBU_GLOBAL_SOFT_RST_BIT;
+
+ regmap_update_bits(regmap, MVEBU_RSTOUTN_MASK_REG, bit, bit);
+ regmap_update_bits(regmap, MVEBU_SYS_SOFT_RST_REG, bit, bit);
+
+ /* Loop while waiting for the reset */
+ while (1)
+ ;
+
+ return 0;
+}
+
+static struct sysreset_ops mvebu_sysreset_ops = {
+ .request = mvebu_sysreset_request,
+};
+
+U_BOOT_DRIVER(mvebu_sysreset) = {
+ .name = "mvebu-sysreset",
+ .id = UCLASS_SYSRESET,
+ .ops = &mvebu_sysreset_ops,
+};
+
+#endif /* IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_SYSRESET) */
+
static int mvebu_syscon_bind(struct udevice *dev)
{
+ int ret = 0;
+
/* bind also mvebu-reset, with the same ofnode */
- return device_bind_driver_to_node(dev, "mvebu-reset", "mvebu-reset",
- dev_ofnode(dev), NULL);
+ if (IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_RESET)) {
+ ret = device_bind_driver_to_node(dev, "mvebu-reset",
+ "mvebu-reset", dev_ofnode(dev),
+ NULL);
+ if (ret < 0)
+ return ret;
+ }
+
+ /* bind also mvebu-sysreset, with the same ofnode */
+ if (IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_SYSRESET)) {
+ ret = device_bind_driver_to_node(dev, "mvebu-sysreset",
+ "mvebu-sysreset",
+ dev_ofnode(dev), NULL);
+ if (ret < 0)
+ return ret;
+ }
+
+ return ret;
}
static const struct udevice_id mvebu_syscon_of_match[] = {