board: freescale: p1_p2_rdb_pc: Fix page attributes for second 1G SDRAM map

Like for first 1G SDRAM map, do not enable Caching-inhibited nor Guarded
attribute for second 1G SDRAM mapping. Whole 2G SDRAM should use caches and
also allow speculative loading (by not setting Guarded attribute).

Also enable Memory Coherency attribute for second 1G SDRAM map. In commit
316f0d0f8f3c ("powerpc: mpc85xx: Fix static TLB table for SDRAM") it was
enabled for all SDRAM maps on all other boards, just missed this one case.

As a last thing, first 1G SDRAM map has wrong comment, so adjust it.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>

diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
index fcd7a55199f0eac055ba636d2d2493d87ca6bb34..5931ec650bd87270feb27d00877ebc5ff127bf92 100644 (file)
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -79,16 +79,16 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 #if defined(CONFIG_SYS_RAMBOOT) || \
        (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
-       /* *I*G - eSDHC/eSPI/NAND boot */
+       /* **M** - 1G DDR for eSDHC/eSPI/NAND boot */
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
                        0, 8, BOOKE_PAGESZ_1G, 1),
 
 #if defined(CONFIG_TARGET_P1020RDB_PD)
-       /* 2G DDR on P1020MBG, map the second 1G */
+       /* **M** - 2G DDR on P1020MBG, map the second 1G */
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
                        CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
-                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
                        0, 9, BOOKE_PAGESZ_1G, 1),
 #endif
 #endif /* RAMBOOT/SPL */