arm: zynq: Label whole PL part as fpga_full region

This will simplify dt overlay structure for the whole PL.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>

diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 34fc6e5f8936dd5976029e1ea237f45ef180e521..f993e19ef2801d374c9b4e654626d5b9682caca6 100644 (file)
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -38,6 +38,14 @@
                };
        };
 
+       fpga_full: fpga-full {
+               compatible = "fpga-region";
+               fpga-mgr = <&devcfg>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+       };
+
        pmu@f8891000 {
                compatible = "arm,cortex-a9-pmu";
                interrupts = <0 5 4>, <0 6 4>;