]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
ARM: mvebu: x530: clearfog: Add ODT configuration
authorChris Packham <judge.packham@gmail.com>
Tue, 1 Mar 2022 00:53:23 +0000 (13:53 +1300)
committerStefan Roese <sr@denx.de>
Fri, 4 Mar 2022 07:38:05 +0000 (08:38 +0100)
Commit 369e532691e0 ("ddr: marvell: a38x: allow board specific ODT
configuration") added the odt_config member to struct
mv_ddr_topology_map ahead of the clk_enable and ck_delay members. This
means that any boards that configured either of clk_enable or ck_delay
needed to have their board topology updated. This affects the x530 and
clearfog boards. Other A38x boards don't touch any of the trailing
members of mv_ddr_topology_map so don't need updating.

Fixes: 369e532691e0 ("ddr: marvell: a38x: allow board specific ODT configuration")
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
board/alliedtelesis/x530/x530.c
board/solidrun/clearfog/clearfog.c

index 8b31045a0743c83bb7b0e717d253bb83952ca410..c0ec2afa30112d1eb4f3f2b6b550ce3e864c68e3 100644 (file)
@@ -73,6 +73,7 @@ static struct mv_ddr_topology_map board_topology_map = {
        {0},                            /* timing parameters */
        { {0} },                        /* electrical configuration */
        {0},                            /* electrical parameters */
+       0,                              /* ODT configuration */
        0,                              /* Clock enable mask */
        160                             /* Clock delay */
 };
index c920cf8d6b5025a89e018c4e5d1bd66f610dc5cc..03adb591d82682e847932c8bd10f93fe826ad08b 100644 (file)
@@ -147,6 +147,7 @@ static struct mv_ddr_topology_map board_topology_map = {
        {0},                            /* timing parameters */
        { {0} },                        /* electrical configuration */
        {0,},                           /* electrical parameters */
+       0,                              /* ODT configuration */
        0x3,                            /* clock enable mask */
 };