ARM: DRA72: disable workaround for 801819

DRA72x processor variants are single core and it does not export ACP[1].
Hence, we have no source for generating an external snoop requests which
appear to be key to the deadlock in DRA72x design.

Since we build the same image for DRA74x and DRA72x platforms, lets
runtime detect and disable the workaround (in favor of performance) on
DRA72x platforms.

[1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0438i/BABIAJAG.html

Suggested-by: Richard Woodruff <r-woodruff2@ti.com>
Suggested-by: Brad Griffis <bgriffis@ti.com>
Reviewed-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>

diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
index bc19aebc6db7d9b084b54763cfffda551ecf9088..22e0829a6a0c2482328f6136ec1e6cf2160586bc 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -422,5 +422,16 @@ void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
 void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
                          u32 cpu_variant, u32 cpu_rev)
 {
+
+#ifdef CONFIG_ARM_ERRATA_801819
+       /*
+        * DRA72x processors are uniprocessors and DONOT have
+        * ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency
+        * Extensions) Hence the erratum workaround is not applicable for
+        * DRA72x processors.
+        */
+       if (is_dra72x())
+               acr &= ~((0x3 << 23) | (0x3 << 25));
+#endif
        omap_smc1(OMAP5_SERVICE_ACR_SET, acr);
 }