sunxi: H6: Add DDR3 DRAM delay values

Add some basic line delay values to be used with DDR3 DRAM chips on
some H6 TV boxes.
Taken from a register dump after boot0 initialised the DRAM.
Put them as the default delay values for DDR3 DRAM until we know better.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>

diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c
index 17649ffbf9cbc08cd1f032eb65184f3feaaf240b..2a8275da3a6ba306016a17ff14ffdf1d1d174dbf 100644 (file)
--- a/arch/arm/mach-sunxi/dram_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c
@@ -594,17 +594,28 @@ unsigned long mctl_calc_size(struct dram_para *para)
        return (1ULL << (para->cols + para->rows + 3)) * 4 * para->ranks;
 }
 
-#define SUN50I_H6_DX_WRITE_DELAYS                              \
+#define SUN50I_H6_LPDDR3_DX_WRITE_DELAYS                       \
        {{  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 },    \
         {  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 },    \
         {  0,  0,  0,  0,  0,  0,  0,  0,  0,  4,  4,  0 },    \
         {  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 }}
-#define SUN50I_H6_DX_READ_DELAYS                                       \
+#define SUN50I_H6_LPDDR3_DX_READ_DELAYS                                        \
        {{  4,  4,  4,  4,  4,  4,  4,  4,  4,  0,  0,  0,  0,  0 },    \
         {  4,  4,  4,  4,  4,  4,  4,  4,  4,  0,  0,  0,  0,  0 },    \
         {  4,  4,  4,  4,  4,  4,  4,  4,  4,  0,  0,  0,  0,  0 },    \
         {  4,  4,  4,  4,  4,  4,  4,  4,  4,  0,  0,  0,  0,  0 }}
 
+#define SUN50I_H6_DDR3_DX_WRITE_DELAYS                         \
+       {{  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 },    \
+        {  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 },    \
+        {  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 },    \
+        {  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 }}
+#define SUN50I_H6_DDR3_DX_READ_DELAYS                                  \
+       {{  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 },    \
+        {  4,  4,  4,  4,  4,  4,  4,  4,  4,  0,  0,  0,  0,  0 },    \
+        {  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 },    \
+        {  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 }}
+
 unsigned long sunxi_dram_init(void)
 {
        struct sunxi_mctl_com_reg * const mctl_com =
@@ -616,12 +627,12 @@ unsigned long sunxi_dram_init(void)
                .rows = 14,
 #ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3
                .type = SUNXI_DRAM_TYPE_LPDDR3,
-               .dx_read_delays  = SUN50I_H6_DX_READ_DELAYS,
-               .dx_write_delays = SUN50I_H6_DX_WRITE_DELAYS,
+               .dx_read_delays  = SUN50I_H6_LPDDR3_DX_READ_DELAYS,
+               .dx_write_delays = SUN50I_H6_LPDDR3_DX_WRITE_DELAYS,
 #elif defined(CONFIG_SUNXI_DRAM_H6_DDR3_1333)
                .type = SUNXI_DRAM_TYPE_DDR3,
-               .dx_read_delays  = SUN50I_H6_DX_READ_DELAYS,
-               .dx_write_delays = SUN50I_H6_DX_WRITE_DELAYS,
+               .dx_read_delays  = SUN50I_H6_DDR3_DX_READ_DELAYS,
+               .dx_write_delays = SUN50I_H6_DDR3_DX_WRITE_DELAYS,
 #endif
        };