rockchip: rk3399: Add Rock960 CE board support

Add board support for Rock960 CE board from Vamrs. This board utilizes
common Rock960 family support.

Following peripherals are tested and known to work:
* USB 2.0
* MMC

This commit also adds DDR configuration for LPDDR3-2GiB-1600MHz which
is being used on the board.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c5960d3f928dd4928969da8dc4f2a1a02b2756ec..dc319bc23669ab38fad44406857be53ca2176c67 100644 (file)
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
        rk3399-puma-ddr1333.dtb \
        rk3399-puma-ddr1600.dtb \
        rk3399-puma-ddr1866.dtb \
+       rk3399-rock960.dtb \
        rv1108-evb.dtb
 dtb-$(CONFIG_ARCH_MESON) += \
        meson-gxbb-nanopi-k2.dtb \

diff --git a/arch/arm/dts/rk3399-rock960.dts b/arch/arm/dts/rk3399-rock960.dts
new file mode 100644 (file)
index 0000000..25c58b4
--- /dev/null
+++ b/arch/arm/dts/rk3399-rock960.dts
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ */
+
+/dts-v1/;
+#include "rk3399-rock960.dtsi"
+#include "rk3399-sdram-lpddr3-2GB-1600.dtsi"
+
+/ {
+       model = "96boards Rock960";
+       compatible = "vamrs,rock960", "rockchip,rk3399";
+
+       chosen {
+               stdout-path = "serial2:1500000n8";
+       };
+};
+
+&pcie0 {
+       ep-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>;
+};
+
+&pinctrl {
+       pcie {
+               pcie_drv: pcie-drv {
+                       rockchip,pins =
+                               <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+                       };
+       };
+
+       usb2 {
+               host_vbus_drv: host-vbus-drv {
+                       rockchip,pins =
+                               <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
+};
+
+&vcc3v3_pcie {
+       gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>;
+};
+
+&vcc5v0_host {
+       gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
+};

diff --git a/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi b/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi
new file mode 100644 (file)
index 0000000..d14e833
--- /dev/null
+++ b/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi
@@ -0,0 +1,1536 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ */
+
+&dmc {
+       rockchip,sdram-params = <
+               0x1
+               0xa
+               0x3
+               0x2
+               0x2
+               0x0
+               0xf
+               0xf
+               1
+               0x1d191519
+               0x14040808
+               0x00000002
+               0x00006226
+               0x00000054
+               0x00000000
+               0x1
+               0xa
+               0x3
+               0x2
+               0x2
+               0x0
+               0xf
+               0xf
+               1
+               0x1d191519
+               0x14040808
+               0x00000002
+               0x00006226
+               0x00000054
+               0x00000000
+               800
+               6
+               2
+               9
+               1
+               0x00000700
+               0x00000000
+               0x00000000
+               0x00000000
+               0x00000000
+               0x00000050
+               0x00027100
+               0x00000320
+               0x00001f40
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+               0x00000050
+               0x00027100
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+               0x01001f40
+               0x00000000
+               0x00000101
+               0x00020100
+               0x000000a0
+               0x00000190
+               0x00000000
+               0x06180000
+               0x00061800
+               0x04000618
+               0x33080004
+               0x280f0622
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+               0x00000000
+               0xe4000000
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+               0x01010000
+               0x00000000
+       >;
+};

diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig
new file mode 100644 (file)
index 0000000..bb10ee9
--- /dev/null
+++ b/configs/rock960-rk3399_defconfig
@@ -0,0 +1,69 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
+CONFIG_TARGET_ROCK960_RK3399=y
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_BAUDRATE=1500000
+CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock960"
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb"
+CONFIG_SYS_PROMPT="rock960 => "
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_ROCKCHIP_RK3399=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_STORAGE=y
+CONFIG_ROCKCHIP_USB2_PHY=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_ERRNO_STR=y