ARM: bcm283x: Define CONFIG_SYS_CACHELINE_SIZE

The cacheline is always 32 bytes for arm1176 CPUs, so define it at board
config level for cache handling code.
The ARM Cortex-A7 has a dcache line size of 64 bytes.

Signed-off-by: Alexander Stein <alexanders83@web.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>

diff --git a/include/configs/rpi.h b/include/configs/rpi.h
index ab2f4db39fec8b81f91de0298d05ca05b973c9ff..86422e390da2d966a15cf4b993c56f7e7966aa72 100644 (file)
--- a/include/configs/rpi.h
+++ b/include/configs/rpi.h
@@ -7,6 +7,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_SYS_CACHELINE_SIZE              32
+
 #include "rpi-common.h"
 
 #endif

diff --git a/include/configs/rpi_2.h b/include/configs/rpi_2.h
index 2e7e74fd563b31797a92e21697409f4464bf317a..13dc8de14315147d798f8074a9e021cf40938125 100644 (file)
--- a/include/configs/rpi_2.h
+++ b/include/configs/rpi_2.h
@@ -9,6 +9,7 @@
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_BCM2836
+#define CONFIG_SYS_CACHELINE_SIZE              64
 
 #include "rpi-common.h"