armv8: lx2160a: add MMU table entries for PCIe

The lx2160a have up to 6 PCIe controllers and have different
address and size of PCIe region.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index db7577b6ed35414e0c6d1330bd887c64ccd55b8f..9801e64867ddc0febb571e8b14568e25f8d29718 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -257,6 +257,20 @@ static struct mm_region final_map[] = {
          PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
        },
+#endif
+#ifdef SYS_PCIE5_PHYS_ADDR
+       { SYS_PCIE5_PHYS_ADDR, SYS_PCIE5_PHYS_ADDR,
+         SYS_PCIE5_PHYS_SIZE,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       },
+#endif
+#ifdef SYS_PCIE6_PHYS_ADDR
+       { SYS_PCIE6_PHYS_ADDR, SYS_PCIE6_PHYS_ADDR,
+         SYS_PCIE6_PHYS_SIZE,
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       },
 #endif
        { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
          CONFIG_SYS_FSL_WRIOP1_SIZE,

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 89124cdb0e3f491fe37e6ce82c098076849a49a7..bdeb62576c7065f2f9f548f9082796d9ccf4c4c0 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -44,6 +44,8 @@
 #define CONFIG_SYS_PCIE2_PHYS_SIZE     0x800000000
 #define CONFIG_SYS_PCIE3_PHYS_SIZE     0x800000000
 #define CONFIG_SYS_PCIE4_PHYS_SIZE     0x800000000
+#define SYS_PCIE5_PHYS_SIZE            0x800000000
+#define SYS_PCIE6_PHYS_SIZE            0x800000000
 #endif
 #define CONFIG_SYS_FSL_WRIOP1_BASE     0x4300000000
 #define CONFIG_SYS_FSL_WRIOP1_SIZE     0x100000000

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 9fab88ab2ffa1904c0bc66c946bd989dcad16f10..c9aa0cad71ac8da9a5f197deb99832af45a324a6 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -167,7 +167,19 @@
 #define CONFIG_SYS_PCIE2_ADDR                  (CONFIG_SYS_IMMR + 0x2500000)
 #define CONFIG_SYS_PCIE3_ADDR                  (CONFIG_SYS_IMMR + 0x2600000)
 #define CONFIG_SYS_PCIE4_ADDR                  (CONFIG_SYS_IMMR + 0x2700000)
-#ifdef CONFIG_ARCH_LS1088A
+#ifdef CONFIG_ARCH_LX2160A
+#define SYS_PCIE5_ADDR                         (CONFIG_SYS_IMMR + 0x2800000)
+#define SYS_PCIE6_ADDR                         (CONFIG_SYS_IMMR + 0x2900000)
+#endif
+
+#ifdef CONFIG_ARCH_LX2160A
+#define CONFIG_SYS_PCIE1_PHYS_ADDR             0x8000000000ULL
+#define CONFIG_SYS_PCIE2_PHYS_ADDR             0x8800000000ULL
+#define CONFIG_SYS_PCIE3_PHYS_ADDR             0x9000000000ULL
+#define CONFIG_SYS_PCIE4_PHYS_ADDR             0x9800000000ULL
+#define SYS_PCIE5_PHYS_ADDR                    0xa000000000ULL
+#define SYS_PCIE6_PHYS_ADDR                    0xa800000000ULL
+#elif CONFIG_ARCH_LS1088A
 #define CONFIG_SYS_PCIE1_PHYS_ADDR             0x2000000000ULL
 #define CONFIG_SYS_PCIE2_PHYS_ADDR             0x2800000000ULL
 #define CONFIG_SYS_PCIE3_PHYS_ADDR             0x3000000000ULL