clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate()

Guard 'parent_rate==0' to prevent 'divide by zero' issue in
clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>

diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index 72e675061548986c0b854e5f0a6f1f710a12c8a0..0cdb9df45d997b84ac4b3a88ea8af7e52440a105 100644 (file)
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -176,13 +176,19 @@ static ulong clk_pllv3_av_set_rate(struct clk *clk, ulong rate)
 {
        struct clk_pllv3 *pll = to_clk_pllv3(clk);
        unsigned long parent_rate = clk_get_parent_rate(clk);
-       unsigned long min_rate = parent_rate * 27;
-       unsigned long max_rate = parent_rate * 54;
+       unsigned long min_rate;
+       unsigned long max_rate;
        u32 val, div;
        u32 mfn, mfd = 1000000;
        u32 max_mfd = 0x3FFFFFFF;
        u64 temp64;
 
+       if (parent_rate == 0)
+               return -EINVAL;
+
+       min_rate = parent_rate * 27;
+       max_rate = parent_rate * 54;
+
        if (rate < min_rate || rate > max_rate)
                return -EINVAL;