arm: omap: sata: move enable sata clocks to enable_basic_clocks()

All the clocks which has to be enabled has to be done in
enable_basic_clocks(), so moving enable sata clock to common
clocks enable function.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c
index 5d956b5b14a38f1cb77da6e417d17219f1143d6c..a8a6b8a869e539106a5e5234b37f5567f273b41e 100644 (file)
--- a/arch/arm/mach-omap2/omap5/hw_data.c
+++ b/arch/arm/mach-omap2/omap5/hw_data.c
@@ -361,6 +361,9 @@ void enable_basic_clocks(void)
                (*prcm)->cm_l4per_gpio6_clkctrl,
                (*prcm)->cm_l4per_gpio7_clkctrl,
                (*prcm)->cm_l4per_gpio8_clkctrl,
+#ifdef CONFIG_SCSI_AHCI_PLAT
+               (*prcm)->cm_l3init_ocp2scp3_clkctrl,
+#endif
                0
        };
 
@@ -378,6 +381,9 @@ void enable_basic_clocks(void)
 
 #ifdef CONFIG_TI_QSPI
                (*prcm)->cm_l4per_qspi_clkctrl,
+#endif
+#ifdef CONFIG_SCSI_AHCI_PLAT
+               (*prcm)->cm_l3init_sata_clkctrl,
 #endif
                0
        };
@@ -411,6 +417,12 @@ void enable_basic_clocks(void)
        setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
 #endif
 
+#ifdef CONFIG_SCSI_AHCI_PLAT
+       /* Enable optional functional clock for SATA */
+       setbits_le32((*prcm)->cm_l3init_sata_clkctrl,
+                    SATA_CLKCTRL_OPTFCLKEN_MASK);
+#endif
+
        /* Enable SCRM OPT clocks for PER and CORE dpll */
        setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
                        OPTFCLKEN_SCRM_PER_MASK);

diff --git a/arch/arm/mach-omap2/sata.c b/arch/arm/mach-omap2/sata.c
index 2c2d1bce363d8dc8059b0607f568c9d77e9d2fb0..0c8268905aa5fae593c6d19358d9cc5067278bd9 100644 (file)
--- a/arch/arm/mach-omap2/sata.c
+++ b/arch/arm/mach-omap2/sata.c
@@ -37,29 +37,6 @@ int init_sata(int dev)
        int ret;
        u32 val;
 
-       u32 const clk_domains_sata[] = {
-               0
-       };
-
-       u32 const clk_modules_hw_auto_sata[] = {
-               (*prcm)->cm_l3init_ocp2scp3_clkctrl,
-               0
-       };
-
-       u32 const clk_modules_explicit_en_sata[] = {
-               (*prcm)->cm_l3init_sata_clkctrl,
-               0
-       };
-
-       do_enable_clocks(clk_domains_sata,
-                        clk_modules_hw_auto_sata,
-                        clk_modules_explicit_en_sata,
-                        0);
-
-       /* Enable optional functional clock for SATA */
-       setbits_le32((*prcm)->cm_l3init_sata_clkctrl,
-                    SATA_CLKCTRL_OPTFCLKEN_MASK);
-
        sata_phy.power_reg = (void __iomem *)(*ctrl)->control_phy_power_sata;
 
        /* Power up the PHY */