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riscv: andesv5: Set default cache line size to 64-bytes
authorYu Chien Peter Lin <peterlin@andestech.com>
Thu, 11 Apr 2024 09:29:45 +0000 (17:29 +0800)
committerLeo Yu-Chi Liang <ycliang@andestech.com>
Wed, 1 May 2024 14:40:00 +0000 (22:40 +0800)
commitfd55792e143f7ec46c5e70a8683183163d8c6878
tree445bc82a325414cb4597c6ab1f4f0c775aad3a1ftree | snapshot
parentff0de1f0557ed7d2dab47ba976a37347a1fdc432commit | diff
riscv: andesv5: Set default cache line size to 64-bytes

The instruction and data cache line sizes of Andes core
are 64-byte. Select SYS_CACHE_SHIFT_6 for RISCV_NDS so
the SYS_CACHELINE_SIZE is enabled with a default value.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
arch/riscv/cpu/andesv5/Kconfig diff | blob | history
My U-Boot fork