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(parent: 5a1a8a6) | patch
riscv: fix the wrong swap value register
authorBrad Kim <brad.kim@semifive.com>
Fri, 13 Nov 2020 11:47:51 +0000 (20:47 +0900)
committerAndes <uboot@andestech.com>
Mon, 14 Dec 2020 07:16:34 +0000 (15:16 +0800)
commitfb33eaa3a26cdc37826390b6db223509230ae8e2
treeb25433aa4126fdba6a61ab50d6afcccdcb60a582tree | snapshot
parent5a1a8a63be8f7262a300eddafb18020926b12fb6commit | diff
riscv: fix the wrong swap value register

Not s2 register, t1 register is correct
Fortunately, it works because t1 register has a garbage value

Signed-off-by: Brad Kim <brad.kim@semifive.com>
Reviewed-by: Lukas Auer <lukas@auer.io>
Reviewed-by: Leo Liang <ycliang@andestech.com>
arch/riscv/cpu/start.S diff | blob | history
My U-Boot fork