]> git.dujemihanovic.xyz Git - u-boot.git/commit
riscv: replace use of callee-saved register in standalone
authorLukas Auer <lukas.auer@aisec.fraunhofer.de>
Fri, 4 Jan 2019 00:37:32 +0000 (01:37 +0100)
committerAndes <uboot@andestech.com>
Tue, 15 Jan 2019 01:36:31 +0000 (09:36 +0800)
commitcbb860f2c89c05c4c1d571f61bb76650db489d7d
tree419f667093fc4c6e353fc4ce06e27a69693dd6fb
parent3c37278ff18577b711b14a1c2fcec37daa959f0a
riscv: replace use of callee-saved register in standalone

Register x19 (s3) is a callee-saved register. It must not be used to
load and jump to exported functions without saving it beforehand.
Replace it with t0, a temporary and caller-saved register.

Change the code comment to reflect this and fix it to correctly list gp
as the register with the pointer to global data.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
examples/standalone/stubs.c