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(parent: ae800aa) | patch
riscv: cache: Implement dcache for cv1800b
authorKongyang Liu <seashell11234455@gmail.com>
Sat, 9 Mar 2024 16:54:57 +0000 (00:54 +0800)
committerLeo Yu-Chi Liang <ycliang@andestech.com>
Tue, 9 Apr 2024 03:30:02 +0000 (11:30 +0800)
commitc21dfcb556e5022766b49a3de4797690869493c7
tree2ce0fe708842901444b0cf468ca1eb6f810a7731tree | snapshot
parentae800aa79a80682080b77d7420c7df8d823431d8commit | diff
riscv: cache: Implement dcache for cv1800b

Add dcache operations invalidate_dcache_range and flush_dcache_range for
cv1800b.

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
arch/riscv/cpu/cv1800b/Makefile diff | blob | history
arch/riscv/cpu/cv1800b/cache.c [new file with mode: 0644] blob
My U-Boot fork