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(parent: 3b00fab) | patch
riscv: Weakly define invalidate_icache_range()
authorSamuel Holland <samuel@sholland.org>
Tue, 31 Oct 2023 05:37:20 +0000 (00:37 -0500)
committerLeo Yu-Chi Liang <ycliang@andestech.com>
Thu, 2 Nov 2023 07:15:54 +0000 (15:15 +0800)
commitbade208b5deb16120c6236e941c6e5f081e86c05
treeedd244a408ee39723cd49de76291b16d8c0aeb88tree | snapshot
parent3b00fab616b1150da745bbb36f6644842a24624fcommit | diff
riscv: Weakly define invalidate_icache_range()

Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a
vendor-specific way to invalidate a portion of the instruction cache.
Allow them to override invalidate_icache_range().

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
arch/riscv/lib/cache.c diff | blob | history
My U-Boot fork