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(parent: 5ce7df1) | patch
Fix wrong QSPI clock calculation for AM4372
authorStefan Mätje <stefan.maetje@esd.eu>
Tue, 30 Nov 2021 00:06:56 +0000 (01:06 +0100)
committerTom Rini <trini@konsulko.com>
Sun, 16 Jan 2022 13:31:03 +0000 (08:31 -0500)
commita6e562fe36b2bae780589a81a11fceb6e1b4a9f7
treeec452c000cdc36d7e3fcf0acc3b0e998e9e5b2d2tree | snapshot
parent5ce7df1078a506f01d63d821b6531fac86e079b9commit | diff
Fix wrong QSPI clock calculation for AM4372

On AM4372 the SPI_GCLK input gets its clock from the PRCM module which
divides the PER_CLKOUTM2 frequency (192MHz) by a fixed factor of 4.
See AM437x Reference Manual in section 27 QSPI >> 27.2 Integration.

The QSPI_FCLK therefore needs to take this factor into account and
becomes (192000000 / 4).

Signed-off-by: Stefan Mätje <stefan.maetje@esd.eu>
drivers/spi/ti_qspi.c diff | blob | history
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