]> git.dujemihanovic.xyz Git - u-boot.git/commit
riscv: Make SiFive HiFive Unleashed board boot again
authorBin Meng <bin.meng@windriver.com>
Mon, 20 Jul 2020 06:17:07 +0000 (23:17 -0700)
committerAndes <uboot@andestech.com>
Fri, 24 Jul 2020 06:55:04 +0000 (14:55 +0800)
commita0018fc8209c0bf7188592527fc0a7d459b9c144
tree2b5931250ac14ef6f7d2004b42c1a86641cd2884
parent5d3a21df6694ebd66d5c34c9d62a26edc7456fc7
riscv: Make SiFive HiFive Unleashed board boot again

Commit 40686c394e53 ("riscv: Clean up IPI initialization code")
caused U-Boot failed to boot on SiFive HiFive Unleashed board.

The codes inside arch_cpu_init_dm() may call U-Boot timer APIs
before the call to riscv_init_ipi(). At that time the timer register
base (e.g.: the SiFive CLINT device in this case) is unknown yet.

It might be the name riscv_init_ipi() that misleads people to only
consider it is related to IPI, but in fact the timer capability is
provided by the same SiFive CLINT device that provides the IPI.
Timer capability is needed for both UP and SMP.

Considering that the original refactor does have benefits, that it
makes the IPI code more similar to U-Boot initialization idioms.
It also removes some quite ugly macros. Let's do the minimal revert
instead of a complete revert, plus a fixes to arch_cpu_init_dm() to
consider the SPL case.

Fixes: 40686c394e53 ("riscv: Clean up IPI initialization code")
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Leo Liang <ycliang@andestech.com>
arch/riscv/cpu/cpu.c
arch/riscv/lib/sifive_clint.c
common/spl/spl_opensbi.c