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(parent: f0cb809) | patch
phy: cadence: Sierra: Update single link PCIe register configuration
authorSwapnil Jakhade <sjakhade@cadence.com>
Fri, 28 Jan 2022 08:11:47 +0000 (13:41 +0530)
committerTom Rini <trini@konsulko.com>
Tue, 8 Feb 2022 16:00:03 +0000 (11:00 -0500)
commit960efc5edce88dda1350f2ca1f92d3f358762112
tree0df4cdad2ffb236b75470a28acfcf39d54a5cd00tree | snapshot
parentf0cb8096d9226d30b95363244287b4524742144dcommit | diff
phy: cadence: Sierra: Update single link PCIe register configuration

Add single link PCIe register configurations for no SSC and internal
SSC. Also, add missing PMA lane registers for external SSC.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
drivers/phy/cadence/phy-cadence-sierra.c diff | blob | history
My U-Boot fork