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(parent: 92226b5) | patch
arm: zynq: Remove fclk-enable property for cse-nor target
authorMichal Simek <michal.simek@xilinx.com>
Fri, 20 Jul 2018 08:16:21 +0000 (10:16 +0200)
committerMichal Simek <michal.simek@xilinx.com>
Mon, 6 Aug 2018 06:44:35 +0000 (08:44 +0200)
commit7996fcca9d401437527d9e9a464cb79965c90c98
tree0be9bfe26a63ffa1f952071407c587b7a1838e39tree | snapshot
parent92226b5a6d00689dce5c1406913ca97b0b89bda9commit | diff
arm: zynq: Remove fclk-enable property for cse-nor target

Mini cse NOR configuration is running without PL that's why there is no
reason to enable clock to PL.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arch/arm/dts/zynq-cse-nor.dts diff | blob | history
My U-Boot fork