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(parent: 13114f3) | patch
phy: atheros: Clarify the intention of ar8021_config
authorVladimir Oltean <vladimir.oltean@nxp.com>
Wed, 6 May 2020 22:11:52 +0000 (00:11 +0200)
committerTom Rini <trini@konsulko.com>
Thu, 7 May 2020 15:05:00 +0000 (11:05 -0400)
commit4d4e4cf7798276bcb047b65cf80fde63fd347903
treef12fdfb7245ee816c55f69124e04a261ee3e9578tree | snapshot
parent13114f38e2ccea9386726d8b9831dfc310589548commit | diff
phy: atheros: Clarify the intention of ar8021_config

Debug register 5 contains TX_CLK DELAY at bit 8 and reserved values at
the other bit positions, just like the other PHYs in the family do.
Therefore, it is not necessary to hardcode the reserved values, but
instead simply follow the read-modify-write procedure from the common
function.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
drivers/net/phy/atheros.c diff | blob | history
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