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(parent: dc73cbe) | patch
iMX6: Disable the L2 before chaning the PL310 latency
authorYe.Li <Ye.Li@freescale.com>
Wed, 20 Aug 2014 09:18:24 +0000 (17:18 +0800)
committerStefano Babic <sbabic@denx.de>
Tue, 9 Sep 2014 14:30:40 +0000 (16:30 +0200)
commit4aa7ac30a7173934f32db466bd4592cd292e7cc9
tree14572029507d437b8ddf842bd1d66c4b2ad233e5tree | snapshot
parentdc73cbe7b05851a3ff76beabdc0589d2b3ebb9a3commit | diff
iMX6: Disable the L2 before chaning the PL310 latency

The Latency parameters of PL310 Tag RAM latency control register and
Data RAM Latency control register are set in L2 cache enable. And
setting these registers must have PL310 NOT enabled.

But when using Plugin mode boot, the PL310 is enabled by bootrom.
The patch disables the PL310 before applying this setting.

Signed-off-by: Ye.Li <Ye.Li@freescale.com>
arch/arm/cpu/armv7/mx6/soc.c diff | blob | history
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