git.dujemihanovic.xyz Git - u-boot.git/commit

]> git.dujemihanovic.xyz Git - u-boot.git/commit

author	Bin Meng <bmeng.cn@gmail.com>
	Wed, 12 Dec 2018 14:12:42 +0000 (06:12 -0800)
committer	Andes <uboot@andestech.com>
	Tue, 18 Dec 2018 01:56:27 +0000 (09:56 +0800)
commit	496262cca63f25408c6715b39cea1747e8ce9b59
tree	c8484b9d177173fa3220163ccace7c0ecb8203c3	tree \| snapshot
parent	4b3f5ed5ac1a4376c29c3010d25049c03de4ed57	commit \| diff

riscv: Fix context restore before returning from trap handler

sp cannot be loaded before restoring other registers.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>

arch/riscv/cpu/mtrap.S

diff | blob | history

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