clk: microchip: mpfs: fix reference clock handling

clk: microchip: mpfs: fix reference clock handling

The original devicetrees for PolarFire SoC messed up & defined the
msspll's output as a fixed-frequency, 600 MHz clock & used that as the
input for the clock controller node. The msspll is not a fixed
frequency clock and later devicetrees handled this properly. Check the
devicetree & if it is one of the fixed ones, register the msspll.
Otherwise, skip registering it & pass the reference clock directly to
the cfg clock registration function so that existing devicetrees are
not broken by this change.

As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for
it, based on the one in Linux.

Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
Tested-by: Padmarao Begari <padmarao.begari@microchip.com>