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ARM: dts: stm32: set PLL4_P to 125Mhz for ETH_CLK for stm32mp157c-odyssey
authorHeesub Shin <heesub@gmail.com>
Sun, 28 Apr 2024 14:24:02 +0000 (23:24 +0900)
committerPatrice Chotard <patrice.chotard@foss.st.com>
Tue, 18 Jun 2024 06:55:52 +0000 (08:55 +0200)
commit2ae44edf1d341db1a0102150e02f463c90d657a0
treebf0d2f8555e5e0f4e082ea29cb834d15f3c4ecf9tree | snapshot
parent69374aa86aa2fd6e301f7e4acfd2f3fb4441c68acommit | diff
ARM: dts: stm32: set PLL4_P to 125Mhz for ETH_CLK for stm32mp157c-odyssey

Odyssey board requires ETH_CLK of 125Mhz. This commit sets PLL4_P/Q/R to
125, 62.5 and 62.5Mhz in respectively.

Signed-off-by: Heesub Shin <heesub@gmail.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi diff | blob | history
My U-Boot fork