]> git.dujemihanovic.xyz Git - u-boot.git/commit
phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC
authorJean-Jacques Hiblot <jjhiblot@ti.com>
Wed, 21 Jul 2021 15:58:38 +0000 (21:28 +0530)
committerLokesh Vutla <lokeshvutla@ti.com>
Tue, 27 Jul 2021 05:27:12 +0000 (10:57 +0530)
commit1a83f9931e052168c225033d9c642112142dab70
tree5f644f4cd55fb339d60664f6ca159f4d719c92ce
parent193c7351624c318a75058df984e0cf653a8498ad
phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC

Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES
wrapper used to configure some of the input signals to the SERDES. It is
used with both Sierra(16G) and Torrent(10G) SERDES. This driver configures
three clock selects (pll0, pll1, dig) and supports resets for each of the
lanes.

This is an adaptation of the linux driver.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-10-kishon@ti.com
drivers/phy/Kconfig
drivers/phy/Makefile
drivers/phy/ti/Kconfig [new file with mode: 0644]
drivers/phy/ti/Makefile [new file with mode: 0644]
drivers/phy/ti/phy-j721e-wiz.c [new file with mode: 0644]