From c30c44e799e1f7d5184c487809edbd612705ba5c Mon Sep 17 00:00:00 2001
From: Dai Okamura <okamura.dai@socionext.com>
Date: Wed, 6 Dec 2017 14:16:32 +0900
Subject: [PATCH] ARM: uniphier: fix SSCPLL init code for LD11 SoC
Commit 682e09ff9f35 ("ARM: uniphier: add PLL init code for LD20 SoC")
missed to write the computed value to the SSCPLLCTRL2 register.
Fixes: 682e09ff9f35 ("ARM: uniphier: add PLL init code for LD20 SoC")
Signed-off-by: Dai Okamura <okamura.dai@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/arm/mach-uniphier/clk/pll-base-ld20.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-uniphier/clk/pll-base-ld20.c b/arch/arm/mach-uniphier/clk/pll-base-ld20.c
index 3aa42f8bfd..45fdf0a322 100644
--- a/arch/arm/mach-uniphier/clk/pll-base-ld20.c
+++ b/arch/arm/mach-uniphier/clk/pll-base-ld20.c
@@ -48,6 +48,7 @@ int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
tmp = readl(base + 4);
tmp &= ~SC_PLLCTRL2_SSC_JK_MASK;
tmp |= (41859 * freq / divn) & SC_PLLCTRL2_SSC_JK_MASK;
+ writel(tmp, base + 4);
udelay(50);
}
--
2.39.5