From: Priyanka Jain <priyanka.jain@nxp.com>
Date: Thu, 3 Nov 2016 12:20:51 +0000 (+0530)
Subject: armv8: ls2080a: Update serdes protocol support
X-Git-Tag: v2025.01-rc5-pxa1908~8109^2~19
X-Git-Url: http://git.dujemihanovic.xyz/img/login.html?a=commitdiff_plain;h=fc35addea2c0fa5add065c5ea09e206d4cba1abd;p=u-boot.git
armv8: ls2080a: Update serdes protocol support
Add these serdes protocols
Serdes1: 0x39, 0x4B, 0x4C, 0x4D
Serdes2: 0x47, 0x57
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
[YS: Revise commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
---
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c
index eaa44a74c5..67d605e38b 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c
@@ -34,6 +34,11 @@ static struct serdes_config serdes1_cfg_tbl[] = {
{0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_D, QSGMII_C, QSGMII_B,
QSGMII_A} },
{0x35, {QSGMII_D, QSGMII_C, QSGMII_B, PCIE2, XFI4, XFI3, XFI2, XFI1 } },
+ {0x39, {SGMII8, SGMII7, SGMII6, PCIE2, SGMII4, SGMII3, SGMII2,
+ PCIE1 } },
+ {0x4B, {PCIE2, PCIE2, PCIE2, PCIE2, XFI4, XFI3, XFI2, XFI1 } },
+ {0x4C, {XFI8, XFI7, XFI6, XFI5, PCIE1, PCIE1, PCIE1, PCIE1 } },
+ {0x4D, {SGMII8, SGMII7, PCIE2, PCIE2, SGMII4, SGMII3, PCIE1, PCIE1 } },
{}
};
static struct serdes_config serdes2_cfg_tbl[] = {
@@ -64,6 +69,7 @@ static struct serdes_config serdes2_cfg_tbl[] = {
SATA2 } },
{0x4A, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1,
SATA2 } },
+ {0x57, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SGMII15, SGMII16 } },
{}
};
diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c
index 95ff68b364..8618506b8b 100644
--- a/board/freescale/ls2080aqds/eth.c
+++ b/board/freescale/ls2080aqds/eth.c
@@ -64,7 +64,7 @@ static int sgmii_riser_phy_addr[] = {
};
/* Slot2 does not have EMI connections */
-#define EMI_NONE 0xFFFFFFFF
+#define EMI_NONE 0xFF
#define EMI1_SLOT1 0
#define EMI1_SLOT2 1
#define EMI1_SLOT3 2
@@ -470,7 +470,49 @@ static void initialize_dpmac_to_slot(void)
}
break;
+ case 0x39:
+ printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
+ serdes1_prtcl);
+ if (hwconfig_f("xqsgmii", env_hwconfig)) {
+ lane_to_slot_fsm1[0] = EMI1_SLOT3;
+ lane_to_slot_fsm1[1] = EMI1_SLOT3;
+ lane_to_slot_fsm1[2] = EMI1_SLOT3;
+ lane_to_slot_fsm1[3] = EMI_NONE;
+ } else {
+ lane_to_slot_fsm1[0] = EMI_NONE;
+ lane_to_slot_fsm1[1] = EMI_NONE;
+ lane_to_slot_fsm1[2] = EMI_NONE;
+ lane_to_slot_fsm1[3] = EMI_NONE;
+ }
+ lane_to_slot_fsm1[4] = EMI1_SLOT3;
+ lane_to_slot_fsm1[5] = EMI1_SLOT3;
+ lane_to_slot_fsm1[6] = EMI1_SLOT3;
+ lane_to_slot_fsm1[7] = EMI_NONE;
+ break;
+
+ case 0x4D:
+ printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
+ serdes1_prtcl);
+ if (hwconfig_f("xqsgmii", env_hwconfig)) {
+ lane_to_slot_fsm1[0] = EMI1_SLOT3;
+ lane_to_slot_fsm1[1] = EMI1_SLOT3;
+ lane_to_slot_fsm1[2] = EMI_NONE;
+ lane_to_slot_fsm1[3] = EMI_NONE;
+ } else {
+ lane_to_slot_fsm1[0] = EMI_NONE;
+ lane_to_slot_fsm1[1] = EMI_NONE;
+ lane_to_slot_fsm1[2] = EMI_NONE;
+ lane_to_slot_fsm1[3] = EMI_NONE;
+ }
+ lane_to_slot_fsm1[4] = EMI1_SLOT3;
+ lane_to_slot_fsm1[5] = EMI1_SLOT3;
+ lane_to_slot_fsm1[6] = EMI_NONE;
+ lane_to_slot_fsm1[7] = EMI_NONE;
+ break;
+
case 0x2A:
+ case 0x4B:
+ case 0x4C:
printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
serdes1_prtcl);
break;
@@ -505,6 +547,38 @@ static void initialize_dpmac_to_slot(void)
lane_to_slot_fsm2[7] = EMI1_SLOT6;
}
break;
+
+ case 0x47:
+ printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
+ serdes2_prtcl);
+ lane_to_slot_fsm2[0] = EMI_NONE;
+ lane_to_slot_fsm2[1] = EMI1_SLOT5;
+ lane_to_slot_fsm2[2] = EMI1_SLOT5;
+ lane_to_slot_fsm2[3] = EMI1_SLOT5;
+
+ if (hwconfig_f("xqsgmii", env_hwconfig)) {
+ lane_to_slot_fsm2[4] = EMI_NONE;
+ lane_to_slot_fsm2[5] = EMI1_SLOT5;
+ lane_to_slot_fsm2[6] = EMI1_SLOT5;
+ lane_to_slot_fsm2[7] = EMI1_SLOT5;
+ }
+ break;
+
+ case 0x57:
+ printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
+ serdes2_prtcl);
+ if (hwconfig_f("xqsgmii", env_hwconfig)) {
+ lane_to_slot_fsm2[0] = EMI_NONE;
+ lane_to_slot_fsm2[1] = EMI_NONE;
+ lane_to_slot_fsm2[2] = EMI_NONE;
+ lane_to_slot_fsm2[3] = EMI_NONE;
+ }
+ lane_to_slot_fsm2[4] = EMI_NONE;
+ lane_to_slot_fsm2[5] = EMI_NONE;
+ lane_to_slot_fsm2[6] = EMI1_SLOT5;
+ lane_to_slot_fsm2[7] = EMI1_SLOT5;
+ break;
+
default:
printf(" %s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
__func__ , serdes2_prtcl);
@@ -537,8 +611,10 @@ void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
switch (serdes1_prtcl) {
case 0x07:
+ case 0x39:
+ case 0x4D:
+ lane = serdes_get_first_lane(FSL_SRDS_1, SGMII1 + dpmac_id - 1);
- lane = serdes_get_first_lane(FSL_SRDS_1, SGMII1 + dpmac_id);
slot = lane_to_slot_fsm1[lane];
switch (++slot) {
@@ -559,6 +635,26 @@ void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
wriop_set_mdio(dpmac_id, bus);
break;
case 3:
+ if (slot == EMI_NONE)
+ return;
+ if (serdes1_prtcl == 0x39) {
+ wriop_set_phy_address(dpmac_id,
+ riser_phy_addr[dpmac_id - 2]);
+ if (dpmac_id >= 6 && hwconfig_f("xqsgmii",
+ env_hwconfig))
+ wriop_set_phy_address(dpmac_id,
+ riser_phy_addr[dpmac_id - 3]);
+ } else {
+ wriop_set_phy_address(dpmac_id,
+ riser_phy_addr[dpmac_id - 2]);
+ if (dpmac_id >= 7 && hwconfig_f("xqsgmii",
+ env_hwconfig))
+ wriop_set_phy_address(dpmac_id,
+ riser_phy_addr[dpmac_id - 3]);
+ }
+ dpmac_info[dpmac_id].board_mux = EMI1_SLOT3;
+ bus = mii_dev_for_muxval(EMI1_SLOT3);
+ wriop_set_mdio(dpmac_id, bus);
break;
case 4:
break;
@@ -579,6 +675,8 @@ serdes2:
case 0x07:
case 0x08:
case 0x49:
+ case 0x47:
+ case 0x57:
lane = serdes_get_first_lane(FSL_SRDS_2, SGMII9 +
(dpmac_id - 9));
slot = lane_to_slot_fsm2[lane];
@@ -597,7 +695,23 @@ serdes2:
wriop_set_mdio(dpmac_id, bus);
break;
case 5:
- break;
+ if (slot == EMI_NONE)
+ return;
+ if (serdes2_prtcl == 0x47) {
+ wriop_set_phy_address(dpmac_id,
+ riser_phy_addr[dpmac_id - 10]);
+ if (dpmac_id >= 14 && hwconfig_f("xqsgmii",
+ env_hwconfig))
+ wriop_set_phy_address(dpmac_id,
+ riser_phy_addr[dpmac_id - 11]);
+ } else {
+ wriop_set_phy_address(dpmac_id,
+ riser_phy_addr[dpmac_id - 11]);
+ }
+ dpmac_info[dpmac_id].board_mux = EMI1_SLOT5;
+ bus = mii_dev_for_muxval(EMI1_SLOT5);
+ wriop_set_mdio(dpmac_id, bus);
+ break;
case 6:
/* Slot housing a SGMII riser card? */
wriop_set_phy_address(dpmac_id,
@@ -691,6 +805,8 @@ void ls2080a_handle_phy_interface_xsgmii(int i)
switch (serdes1_prtcl) {
case 0x2A:
+ case 0x4B:
+ case 0x4C:
/*
* XFI does not need a PHY to work, but to avoid U-Boot use
* default PHY address which is zero to a MAC when it found